{"title":"基于FPGA的时间可预测双核原型","authors":"Satya Mohan Raju Gudidevuni, Wei Zhang","doi":"10.1145/1900008.1900020","DOIUrl":null,"url":null,"abstract":"This paper describes the design and implementation of time-predictable dual-core architecture on Xilinx FPGA. The emphasis is to observe the impact of various cache replacement algorithms on the time-predictability of a high priority thread, in a multi-core architecture. This design is done in verilog and consists of two cores, each with a simple 5-stage in-order pipeline and a private L1-cache. This is further connected to a shared L2 cache and a RAM. The design is synthesized in Xilinx ISE and its performance will be tested on Virtex-6 FPGA.","PeriodicalId":333104,"journal":{"name":"ACM SE '10","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A time-predictable dual-core prototype on FPGA\",\"authors\":\"Satya Mohan Raju Gudidevuni, Wei Zhang\",\"doi\":\"10.1145/1900008.1900020\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the design and implementation of time-predictable dual-core architecture on Xilinx FPGA. The emphasis is to observe the impact of various cache replacement algorithms on the time-predictability of a high priority thread, in a multi-core architecture. This design is done in verilog and consists of two cores, each with a simple 5-stage in-order pipeline and a private L1-cache. This is further connected to a shared L2 cache and a RAM. The design is synthesized in Xilinx ISE and its performance will be tested on Virtex-6 FPGA.\",\"PeriodicalId\":333104,\"journal\":{\"name\":\"ACM SE '10\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-04-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ACM SE '10\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/1900008.1900020\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ACM SE '10","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1900008.1900020","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper describes the design and implementation of time-predictable dual-core architecture on Xilinx FPGA. The emphasis is to observe the impact of various cache replacement algorithms on the time-predictability of a high priority thread, in a multi-core architecture. This design is done in verilog and consists of two cores, each with a simple 5-stage in-order pipeline and a private L1-cache. This is further connected to a shared L2 cache and a RAM. The design is synthesized in Xilinx ISE and its performance will be tested on Virtex-6 FPGA.
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