脉冲锁存器通用移位寄存器的分析与设计

Mr. Dharmesh Dhabliya, Dr.S.A.Sivakumar
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引用次数: 7

摘要

功耗利用率和模区空间是构建低功耗结果时需要考虑的重要边界。利用管道原理,提出了一种低力通用寄存器和四件套计数器的结构。由于翻转失败在一些应用中是一个固有的结构障碍,不同的翻转柠檬在广泛的移动寄存器和4件计数器中被观察和执行。利用管道原理翻转柠檬被视为依赖于强度和区域的相关性。最后,利用管道原理设计了一种低力全包移动寄存器和四件套计数器。所提出的USR和4片计数器以从100 KHz到500MHz的各种时钟速率进行模拟。这些翻转比目鱼的重现,广泛的移动寄存器和4片计数器是利用Tanner装置在180纳米创新完成的。与现有方案相比,USR法向力和PDP分别提高了33%和27%,4片计数器法向力和PDP分别提高了36.9%和30.2%。因此,所提出的方案对于低功耗和精英应用是合理的。
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Analysis and Design of Universal Shift Register Using Pulsed Latches
Power utilization and die region space are the significant boundaries which are considered for structuring low level power outcomes. This paper put forward the structure of low force general move register and 4-piece counter utilizing pipe rationale. Since flip failures are an innate structure hinder in a few applications, different flip lemon are over viewed and executed in widespread move register and 4-piece counter. Flip lemon utilizing pipe rationale is viewed as dependent on the correlation of intensity and region. At last, a low force all inclusive move register and 4-piece counter is planned utilizing pipe rationale. The proposed USR and 4-piece counters are mimicked with various clock rate going from 100 KHz to 500MHz. Re-enactment of these flip flounders, the widespread move register and the 4-piece counters are finished utilizing Tanner device at 180nm innovation. The normal force and the PDP of USR are improved by 33% and 27% and further the normal force and the PDP of 4-piece counter are improved by 36.9% and 30.2% when contrasted and existing plan separately. So the put forward plan is reasonable for low level power and elite applications.
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