Prototyping implementation for low-complexity real-time MPEG-2 variable length encoder

MPEG-2 coder has become a standard core for video compression, and the whole module of variable length code (VLC) is a key component within MPEG-2 system. In this study, a real-time VLC encoder is developed by using discrete logic architecture rather than memory-based. In order to improve the chip efficiency, the codeword bank is constructed by order of codeword consisting of tri-state buffer. Three main VLC codeword tables for MPEG-2 system involved coded block pattern, motion vector and DCT coefficients all are efficiently realized in this work. The prototyping circuit is successfully implemented by using Verilog high-level description language and then fitted into a FPGA chip. The total gate-count can be reduced about 30% compared to the conventional VLC designs.