P. Alou, J. Cobos, J. Uceda, M. Rascon, E. de la Cruz
{"title":"基于自驱动同步整流新方案的低输出电压电信DC/DC变换器设计","authors":"P. Alou, J. Cobos, J. Uceda, M. Rascon, E. de la Cruz","doi":"10.1109/APEC.1999.750470","DOIUrl":null,"url":null,"abstract":"In this paper, the design and experimental results of a very low output voltage DC/DC converter for a specific telecom application (1.5 V, 10 A) is presented and analyzed. Several topologies have been compared and analyzed, not only from the point of view of size (15 W/inch/sup 3/, 10 mm of height) and efficiency (>85%), but also regarding the dynamic response of the converter to supply pulsating loads (80 A//spl mu/s). A new driving scheme for self-driven synchronous rectification (SDSR) is used. It allows use of the standard half bridge topology, which is very suitable for such a wide input voltage range (36 V-72 V).","PeriodicalId":287192,"journal":{"name":"APEC '99. Fourteenth Annual Applied Power Electronics Conference and Exposition. 1999 Conference Proceedings (Cat. No.99CH36285)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"38","resultStr":"{\"title\":\"Design of a low output voltage DC/DC converter for telecom application with a new scheme for self-driven synchronous rectification\",\"authors\":\"P. Alou, J. Cobos, J. Uceda, M. Rascon, E. de la Cruz\",\"doi\":\"10.1109/APEC.1999.750470\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, the design and experimental results of a very low output voltage DC/DC converter for a specific telecom application (1.5 V, 10 A) is presented and analyzed. Several topologies have been compared and analyzed, not only from the point of view of size (15 W/inch/sup 3/, 10 mm of height) and efficiency (>85%), but also regarding the dynamic response of the converter to supply pulsating loads (80 A//spl mu/s). A new driving scheme for self-driven synchronous rectification (SDSR) is used. It allows use of the standard half bridge topology, which is very suitable for such a wide input voltage range (36 V-72 V).\",\"PeriodicalId\":287192,\"journal\":{\"name\":\"APEC '99. Fourteenth Annual Applied Power Electronics Conference and Exposition. 1999 Conference Proceedings (Cat. No.99CH36285)\",\"volume\":\"34 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-03-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"38\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"APEC '99. Fourteenth Annual Applied Power Electronics Conference and Exposition. 1999 Conference Proceedings (Cat. No.99CH36285)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APEC.1999.750470\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"APEC '99. Fourteenth Annual Applied Power Electronics Conference and Exposition. 1999 Conference Proceedings (Cat. No.99CH36285)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APEC.1999.750470","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of a low output voltage DC/DC converter for telecom application with a new scheme for self-driven synchronous rectification
In this paper, the design and experimental results of a very low output voltage DC/DC converter for a specific telecom application (1.5 V, 10 A) is presented and analyzed. Several topologies have been compared and analyzed, not only from the point of view of size (15 W/inch/sup 3/, 10 mm of height) and efficiency (>85%), but also regarding the dynamic response of the converter to supply pulsating loads (80 A//spl mu/s). A new driving scheme for self-driven synchronous rectification (SDSR) is used. It allows use of the standard half bridge topology, which is very suitable for such a wide input voltage range (36 V-72 V).
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
