Pub Date : 1999-03-14DOI: 10.1109/APEC.1999.749733
N. Celanovic, D. Boroyevich
This paper explores the fundamental limitations of neutral-point voltage balancing problem for different loading conditions of three level voltage source inverters. A new model in DQ coordinate frame utilizing current switching functions is developed, as a means to investigate theoretical limitations and lend more intuitive insight into the problem. The low frequency ripple of the neutral point caused by certain loading conditions is observed and quantified.
{"title":"A comprehensive study of neutral-point voltage balancing problem in three-level neutral-point-clamped voltage source PWM inverters","authors":"N. Celanovic, D. Boroyevich","doi":"10.1109/APEC.1999.749733","DOIUrl":"https://doi.org/10.1109/APEC.1999.749733","url":null,"abstract":"This paper explores the fundamental limitations of neutral-point voltage balancing problem for different loading conditions of three level voltage source inverters. A new model in DQ coordinate frame utilizing current switching functions is developed, as a means to investigate theoretical limitations and lend more intuitive insight into the problem. The low frequency ripple of the neutral point caused by certain loading conditions is observed and quantified.","PeriodicalId":287192,"journal":{"name":"APEC '99. Fourteenth Annual Applied Power Electronics Conference and Exposition. 1999 Conference Proceedings (Cat. No.99CH36285)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114662618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-14DOI: 10.1109/APEC.1999.750455
M. Swamy, T. Kume
Insulated gate bipolar transistors (IGBTs) have become the unanimous choice for power semiconductor switches in adjustable speed drives (ASDs), also known as variable frequency drives (VFDs). The most common modulation strategy adopted for motor control in ASDs is pulse width modulation (PWM). In general, the output is modulated at a carrier frequency ranging from 1 kHz to 20 kHz. Recent experience with PWM drives have shown that there exists two distinct application issues: (a) common-mode current and shaft voltage due to common-mode voltage; and (b) line-line overvoltage across stator windings in cases where the distance between motor and the inverter is larger than the critical lead length. The high carrier frequency particularly in small sized VFDs (up to 75 kW), along with fast rise and fall time of the IGBTs employed results in steep fronted common-mode voltage which causes nontrivial common-mode or ground currents to flow. When the distance between the motor and the VFD is long and there exists a mismatch in the cable and motor surge impedance, there is voltage amplification at the motor terminals. This paper focuses on the issue relating to common-mode noise. A new scheme to attenuate the common-mode current is presented. Experimental results showing the effectiveness of the proposed solution is presented.
{"title":"Common-mode current attenuation techniques for use with PWM drives","authors":"M. Swamy, T. Kume","doi":"10.1109/APEC.1999.750455","DOIUrl":"https://doi.org/10.1109/APEC.1999.750455","url":null,"abstract":"Insulated gate bipolar transistors (IGBTs) have become the unanimous choice for power semiconductor switches in adjustable speed drives (ASDs), also known as variable frequency drives (VFDs). The most common modulation strategy adopted for motor control in ASDs is pulse width modulation (PWM). In general, the output is modulated at a carrier frequency ranging from 1 kHz to 20 kHz. Recent experience with PWM drives have shown that there exists two distinct application issues: (a) common-mode current and shaft voltage due to common-mode voltage; and (b) line-line overvoltage across stator windings in cases where the distance between motor and the inverter is larger than the critical lead length. The high carrier frequency particularly in small sized VFDs (up to 75 kW), along with fast rise and fall time of the IGBTs employed results in steep fronted common-mode voltage which causes nontrivial common-mode or ground currents to flow. When the distance between the motor and the VFD is long and there exists a mismatch in the cable and motor surge impedance, there is voltage amplification at the motor terminals. This paper focuses on the issue relating to common-mode noise. A new scheme to attenuate the common-mode current is presented. Experimental results showing the effectiveness of the proposed solution is presented.","PeriodicalId":287192,"journal":{"name":"APEC '99. Fourteenth Annual Applied Power Electronics Conference and Exposition. 1999 Conference Proceedings (Cat. No.99CH36285)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127380179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-14DOI: 10.1109/APEC.1999.749730
J. Suh, C. Choi, D. Hyun
In this paper, a newly developed simplified space vector PWM (SVPWM) method for three-level inverter is presented. The space vector diagram of the three-level inverter is simplified into that of a two-level inverter. So the selection of switching sequence and the calculation of the dwelling time is done as conventional two-level SVPWM method. The control of DC link neutral-point potential is easy to implement. The proposed SVPWM method can be applied to the multi-level inverter. The validity of the new SVPWM method is verified by simulation and experiment with a three-level IGBT inverter.
{"title":"A new simplified space-vector PWM method for three-level inverters","authors":"J. Suh, C. Choi, D. Hyun","doi":"10.1109/APEC.1999.749730","DOIUrl":"https://doi.org/10.1109/APEC.1999.749730","url":null,"abstract":"In this paper, a newly developed simplified space vector PWM (SVPWM) method for three-level inverter is presented. The space vector diagram of the three-level inverter is simplified into that of a two-level inverter. So the selection of switching sequence and the calculation of the dwelling time is done as conventional two-level SVPWM method. The control of DC link neutral-point potential is easy to implement. The proposed SVPWM method can be applied to the multi-level inverter. The validity of the new SVPWM method is verified by simulation and experiment with a three-level IGBT inverter.","PeriodicalId":287192,"journal":{"name":"APEC '99. Fourteenth Annual Applied Power Electronics Conference and Exposition. 1999 Conference Proceedings (Cat. No.99CH36285)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127510841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-14DOI: 10.1109/APEC.1999.750443
F. Tao, J. Qian, F. Lee, N. Onishi
The charge pump power factor correction (CPPFC) electronic ballast circuit has become an attractive topological family for ballasting fluorescent lamps because it employs a charging capacitor instead of bulky inductor to implement the power factor correction (PFC). Several topologies have been previously proposed. Based on the different mechanism to achieve PFC, three types, namely, voltage source type CPPFC (VS-CPPFC), current source type CPPFC (CS-CPPFC), and combined voltage source and current source type CPPFC (VSCS-CPPFC) electronic ballast can be classified. These three types of CPPFC electronic ballast have different electrical characteristics, such as different start-up bus voltages, etc. Mathematical analysis is given in this paper based on the study of six typical CPPFC electronic ballast circuits. Then a comparison among these circuits in terms of power factor, DC bus voltage stress at preheat, start-up, and steady state modes, current stress at steady state, and lamp current crest factor is presented. The experimental results are provided for verification.
{"title":"A comparative study of a family of charge pump power factor correction electronic ballasts","authors":"F. Tao, J. Qian, F. Lee, N. Onishi","doi":"10.1109/APEC.1999.750443","DOIUrl":"https://doi.org/10.1109/APEC.1999.750443","url":null,"abstract":"The charge pump power factor correction (CPPFC) electronic ballast circuit has become an attractive topological family for ballasting fluorescent lamps because it employs a charging capacitor instead of bulky inductor to implement the power factor correction (PFC). Several topologies have been previously proposed. Based on the different mechanism to achieve PFC, three types, namely, voltage source type CPPFC (VS-CPPFC), current source type CPPFC (CS-CPPFC), and combined voltage source and current source type CPPFC (VSCS-CPPFC) electronic ballast can be classified. These three types of CPPFC electronic ballast have different electrical characteristics, such as different start-up bus voltages, etc. Mathematical analysis is given in this paper based on the study of six typical CPPFC electronic ballast circuits. Then a comparison among these circuits in terms of power factor, DC bus voltage stress at preheat, start-up, and steady state modes, current stress at steady state, and lamp current crest factor is presented. The experimental results are provided for verification.","PeriodicalId":287192,"journal":{"name":"APEC '99. Fourteenth Annual Applied Power Electronics Conference and Exposition. 1999 Conference Proceedings (Cat. No.99CH36285)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125924707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-14DOI: 10.1109/APEC.1999.750497
J. Itoh, K. Fujita
This paper proposes two novel circuits which realize a unity input power factor single-phase to three-phase power converter with a motor load. The power supply is connected to the neutral point of the motor, and the three-phase inverter is controlled to act also as a virtual AC/DC converter leg. This virtual leg is controlled by zero-vectors of the three-phase inverter. The main features of these circuits are: (i) no inductive components are required; and (ii) a reduction in number of switching devices compared with conventional topologies. A full-bridge power converter can be built using the same number of switching devices as the conventional half-bridge, and with no need for a capacitive leg with accessible neutral point. In this paper, the full-bridge type of the proposed circuit is experimentally tested using a 750 W induction motor as load.
{"title":"Novel unity power factor circuits using zero-vector control for single-phase input system","authors":"J. Itoh, K. Fujita","doi":"10.1109/APEC.1999.750497","DOIUrl":"https://doi.org/10.1109/APEC.1999.750497","url":null,"abstract":"This paper proposes two novel circuits which realize a unity input power factor single-phase to three-phase power converter with a motor load. The power supply is connected to the neutral point of the motor, and the three-phase inverter is controlled to act also as a virtual AC/DC converter leg. This virtual leg is controlled by zero-vectors of the three-phase inverter. The main features of these circuits are: (i) no inductive components are required; and (ii) a reduction in number of switching devices compared with conventional topologies. A full-bridge power converter can be built using the same number of switching devices as the conventional half-bridge, and with no need for a capacitive leg with accessible neutral point. In this paper, the full-bridge type of the proposed circuit is experimentally tested using a 750 W induction motor as load.","PeriodicalId":287192,"journal":{"name":"APEC '99. Fourteenth Annual Applied Power Electronics Conference and Exposition. 1999 Conference Proceedings (Cat. No.99CH36285)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126056444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-14DOI: 10.1109/APEC.1999.749700
G. Spiazzi, J. Pomilio
The effects of a nonnegligible source impedance, due to the presence of an input EMI filter, on the stability of power factor preregulators with average current control are analyzed by using a state space averaged model. The modeling allows to derive a simple expression for the loop gain in terms of the converter current loop gain. The overall system stability is studied for boost, Cuk and SEPIC PFP topologies. Based on this model, a simple modification of the standard current control loop is proposed which increases the converter robustness. Comparison between model forecasts and experimental measurements is carried out using two prototypes: one based on the boost topology and the other based on the SEPIC topology both rated at 600 W. Finally, the model accuracy is investigated with measurements at different current loop bandwidths.
{"title":"Interaction between EMI filter and power factor preregulators with average current control: analysis and design considerations","authors":"G. Spiazzi, J. Pomilio","doi":"10.1109/APEC.1999.749700","DOIUrl":"https://doi.org/10.1109/APEC.1999.749700","url":null,"abstract":"The effects of a nonnegligible source impedance, due to the presence of an input EMI filter, on the stability of power factor preregulators with average current control are analyzed by using a state space averaged model. The modeling allows to derive a simple expression for the loop gain in terms of the converter current loop gain. The overall system stability is studied for boost, Cuk and SEPIC PFP topologies. Based on this model, a simple modification of the standard current control loop is proposed which increases the converter robustness. Comparison between model forecasts and experimental measurements is carried out using two prototypes: one based on the boost topology and the other based on the SEPIC topology both rated at 600 W. Finally, the model accuracy is investigated with measurements at different current loop bandwidths.","PeriodicalId":287192,"journal":{"name":"APEC '99. Fourteenth Annual Applied Power Electronics Conference and Exposition. 1999 Conference Proceedings (Cat. No.99CH36285)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126108009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-14DOI: 10.1109/APEC.1999.749500
J. Mulkern, G. T. Lommasson
Designing products for the space environment has its own set of rules and concerns, but by understanding this knowledge you too can put products into space. This paper presents some of the concerns and criteria for power supply/power system design intended for space platforms. This paper first describes the space environment and some of the areas of note to a power supply designer. Next some of the system level issues of space platforms is discussed.
{"title":"Out of this world products-designing for space","authors":"J. Mulkern, G. T. Lommasson","doi":"10.1109/APEC.1999.749500","DOIUrl":"https://doi.org/10.1109/APEC.1999.749500","url":null,"abstract":"Designing products for the space environment has its own set of rules and concerns, but by understanding this knowledge you too can put products into space. This paper presents some of the concerns and criteria for power supply/power system design intended for space platforms. This paper first describes the space environment and some of the areas of note to a power supply designer. Next some of the system level issues of space platforms is discussed.","PeriodicalId":287192,"journal":{"name":"APEC '99. Fourteenth Annual Applied Power Electronics Conference and Exposition. 1999 Conference Proceedings (Cat. No.99CH36285)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123277179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-14DOI: 10.1109/APEC.1999.750500
Y. Panov, M. Jovanovic
The paper presents the design and performance evaluation of two-stage AC power adapters for notebook computers which deliver 70 W from the universal line. Three versions of the flyback power converter, as well as the PWM and resonant half-bridge power converter were evaluated and compared with respect to their efficiency, component stress, output filter size and complexity.
{"title":"Performance evaluation of 70-W two-stage adapters for notebook computers","authors":"Y. Panov, M. Jovanovic","doi":"10.1109/APEC.1999.750500","DOIUrl":"https://doi.org/10.1109/APEC.1999.750500","url":null,"abstract":"The paper presents the design and performance evaluation of two-stage AC power adapters for notebook computers which deliver 70 W from the universal line. Three versions of the flyback power converter, as well as the PWM and resonant half-bridge power converter were evaluated and compared with respect to their efficiency, component stress, output filter size and complexity.","PeriodicalId":287192,"journal":{"name":"APEC '99. Fourteenth Annual Applied Power Electronics Conference and Exposition. 1999 Conference Proceedings (Cat. No.99CH36285)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125544541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-14DOI: 10.1109/APEC.1999.750466
J. Cobos, P. Alou, Ó. García, J. Uceda, M. Rascon
Self-driven synchronous rectification (SDSR) is a very good technique to improve efficiency and thermal management in low output voltage converters. In this paper, a new scheme to drive the synchronous rectifiers (SRs) is proposed. It allows for maintaining the SRs on even when the voltage in the transformer is zero, which is impossible to do in traditional self-driven approaches. It also makes possible to drive properly the SRs even for applications where output voltage is lower than 3.3 V, namely 1.5 V. Furthermore, driving losses are very low, since the discharge of one MOSFET is used to charge the other and vice versa. This scheme has been validated in two prototypes.
{"title":"New driving scheme for self driven synchronous rectifiers","authors":"J. Cobos, P. Alou, Ó. García, J. Uceda, M. Rascon","doi":"10.1109/APEC.1999.750466","DOIUrl":"https://doi.org/10.1109/APEC.1999.750466","url":null,"abstract":"Self-driven synchronous rectification (SDSR) is a very good technique to improve efficiency and thermal management in low output voltage converters. In this paper, a new scheme to drive the synchronous rectifiers (SRs) is proposed. It allows for maintaining the SRs on even when the voltage in the transformer is zero, which is impossible to do in traditional self-driven approaches. It also makes possible to drive properly the SRs even for applications where output voltage is lower than 3.3 V, namely 1.5 V. Furthermore, driving losses are very low, since the discharge of one MOSFET is used to charge the other and vice versa. This scheme has been validated in two prototypes.","PeriodicalId":287192,"journal":{"name":"APEC '99. Fourteenth Annual Applied Power Electronics Conference and Exposition. 1999 Conference Proceedings (Cat. No.99CH36285)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116170768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-14DOI: 10.1109/APEC.1999.749763
V. Cárdenas, C. Nuñez, N. Vázquez
This paper presents a three-phase shunt active power filter controlled by three different control strategies using a digital signal processor (DSP). The control techniques analyzed and compared are: sliding mode control (SMC), proportional-integral control (PI), and sliding mode control with proportional-integral controller (SMC-PI). Analysis and modeling of the shunt active power filter as well as simulation and experimental results are presented. The results show that the SMC controller has a better performance than PI and SMC-PI, allowing a low THD in the AC mains current and a fast transient response.
{"title":"Analysis and evaluation of control techniques for active power filters: sliding mode control and proportional-integral control","authors":"V. Cárdenas, C. Nuñez, N. Vázquez","doi":"10.1109/APEC.1999.749763","DOIUrl":"https://doi.org/10.1109/APEC.1999.749763","url":null,"abstract":"This paper presents a three-phase shunt active power filter controlled by three different control strategies using a digital signal processor (DSP). The control techniques analyzed and compared are: sliding mode control (SMC), proportional-integral control (PI), and sliding mode control with proportional-integral controller (SMC-PI). Analysis and modeling of the shunt active power filter as well as simulation and experimental results are presented. The results show that the SMC controller has a better performance than PI and SMC-PI, allowing a low THD in the AC mains current and a fast transient response.","PeriodicalId":287192,"journal":{"name":"APEC '99. Fourteenth Annual Applied Power Electronics Conference and Exposition. 1999 Conference Proceedings (Cat. No.99CH36285)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122738870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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