一种用于电路交换片上网络的紧凑高性能开关

2006 IEEE International SOC Conference Pub Date : 1900-01-01 DOI:10.1109/SOCC.2006.283842

Phi-Hung Pham, Yogendera Kumar, Chulwoo Kim

{"title":"一种用于电路交换片上网络的紧凑高性能开关","authors":"Phi-Hung Pham, Yogendera Kumar, Chulwoo Kim","doi":"10.1109/SOCC.2006.283842","DOIUrl":null,"url":null,"abstract":"Compact switch architecture and its fast path-setup scheme for circuit-switched on chip network adopting 4times4 torus topology has been presented. Proposed switch has been synthesized and analyzed using 0.13 mum CMOS process technology. Performance evaluation shows considerable energy efficiency and almost 5 times smaller area compared to the other switches.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A Compact and High Performance Switch for Circuit-Switched Network-On-Chip\",\"authors\":\"Phi-Hung Pham, Yogendera Kumar, Chulwoo Kim\",\"doi\":\"10.1109/SOCC.2006.283842\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Compact switch architecture and its fast path-setup scheme for circuit-switched on chip network adopting 4times4 torus topology has been presented. Proposed switch has been synthesized and analyzed using 0.13 mum CMOS process technology. Performance evaluation shows considerable energy efficiency and almost 5 times smaller area compared to the other switches.\",\"PeriodicalId\":345714,\"journal\":{\"name\":\"2006 IEEE International SOC Conference\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE International SOC Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCC.2006.283842\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE International SOC Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC.2006.283842","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 4

摘要

提出了采用4倍4环面拓扑的片上电路交换网络的紧凑开关结构及其快速路径设置方案。采用0.13 μ m CMOS工艺技术对所提出的开关进行了合成和分析。性能评估显示出相当高的能源效率和几乎比其他开关小5倍的面积。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

A Compact and High Performance Switch for Circuit-Switched Network-On-Chip

Compact switch architecture and its fast path-setup scheme for circuit-switched on chip network adopting 4times4 torus topology has been presented. Proposed switch has been synthesized and analyzed using 0.13 mum CMOS process technology. Performance evaluation shows considerable energy efficiency and almost 5 times smaller area compared to the other switches.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2006 IEEE International SOC Conference

自引率

0.00%

发文量

期刊最新文献

Architecture for Energy Efficient Sphere Decoding Design of Low Power Digital Phase Lock Loops A Novel 8-Phase PLL Design for PWM Scheme in High Speed I/O Circuits Interrupt Communication on the SegBus platform A Detailed Vth-Variation Analysis for Sub-100-nm Embedded SRAM Design