Peng Deng, Fabio Cremona, Qi Zhu, M. Natale, Haibo Zeng
{"title":"基于模型的汽车CPS综合流程","authors":"Peng Deng, Fabio Cremona, Qi Zhu, M. Natale, Haibo Zeng","doi":"10.1145/2735960.2735972","DOIUrl":null,"url":null,"abstract":"Synchronous reactive models are used by automotive suppliers to develop functionality delivered as AUTOSAR components to system integrators (OEMs). Integrators must then generate a task implementation from runnables in AUTOSAR components and deploy tasks onto CPU cores, while preserving timing and resource constraints. In this work, we propose an integrated synthesis flow that addresses both sides of the supply chain. On the supplier side, from synchronous models, we generate AUTOSAR runnables that promote reuse and ease the job of finding schedulable implementations. On the integrator side, we find the mapping of runnables onto tasks and allocation of tasks on cores that satisfy the timing constraints and are memory efficient.","PeriodicalId":344612,"journal":{"name":"Proceedings of the ACM/IEEE Sixth International Conference on Cyber-Physical Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"21","resultStr":"{\"title\":\"A model-based synthesis flow for automotive CPS\",\"authors\":\"Peng Deng, Fabio Cremona, Qi Zhu, M. Natale, Haibo Zeng\",\"doi\":\"10.1145/2735960.2735972\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Synchronous reactive models are used by automotive suppliers to develop functionality delivered as AUTOSAR components to system integrators (OEMs). Integrators must then generate a task implementation from runnables in AUTOSAR components and deploy tasks onto CPU cores, while preserving timing and resource constraints. In this work, we propose an integrated synthesis flow that addresses both sides of the supply chain. On the supplier side, from synchronous models, we generate AUTOSAR runnables that promote reuse and ease the job of finding schedulable implementations. On the integrator side, we find the mapping of runnables onto tasks and allocation of tasks on cores that satisfy the timing constraints and are memory efficient.\",\"PeriodicalId\":344612,\"journal\":{\"name\":\"Proceedings of the ACM/IEEE Sixth International Conference on Cyber-Physical Systems\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-04-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"21\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the ACM/IEEE Sixth International Conference on Cyber-Physical Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/2735960.2735972\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the ACM/IEEE Sixth International Conference on Cyber-Physical Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/2735960.2735972","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Synchronous reactive models are used by automotive suppliers to develop functionality delivered as AUTOSAR components to system integrators (OEMs). Integrators must then generate a task implementation from runnables in AUTOSAR components and deploy tasks onto CPU cores, while preserving timing and resource constraints. In this work, we propose an integrated synthesis flow that addresses both sides of the supply chain. On the supplier side, from synchronous models, we generate AUTOSAR runnables that promote reuse and ease the job of finding schedulable implementations. On the integrator side, we find the mapping of runnables onto tasks and allocation of tasks on cores that satisfy the timing constraints and are memory efficient.