6位CMOS数字射频存储器的设计

Proceedings of the IEEE 1991 National Aerospace and Electronics Conference NAECON 1991 Pub Date : 1991-05-20 DOI:10.1109/NAECON.1991.165727

G. Kranz, M. Mehalic

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引用次数: 2

摘要

介绍了在单集成电路上实现数字射频存储器(DRFM)的方法。完成了DRFM的VHSIC硬件描述语言(VHDL)模型，并用于DRFM体系结构的VLSI组件的设计。该模型执行指定的时移和频移函数。具有1k内存、控制单元和数字单边带调制器(DSSM)的DRFM已放置在硅单芯片布局设计上。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Design of a 6-bit CMOS digital radio frequency memory

The authors describe the implementation of a digital radio frequency memory (DRFM) on a single integrated circuit. A VHSIC Hardware Description Language (VHDL) model of the DRFM was completed and used to design the VLSI components of the DRFM architecture. The model performed the specified time and frequency shift functions. A DRFM, with a 1 K memory, a control unit, and a digital single-sideband modulator (DSSM) has been placed onto a silicon single chip layout design.<>

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Proceedings of the IEEE 1991 National Aerospace and Electronics Conference NAECON 1991

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