用于嵌入式安全应用的基于配对的低功耗加密加速器

2009 IEEE International SOC Conference (SOCC) Pub Date : 2009-09-01 DOI:10.1109/SOCCON.2009.5398017

T. English, Maurice Keller, K. L. Man, E. Popovici, M. Schellekens, W. Marnane

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引用次数: 23

摘要

我们报告了基于配对的加密的IP核的实现。该核心在域GF(2251)上执行称为Tate配对的椭圆曲线加密操作。在本文中，我们描述了该设计在台积电65nm GP CMOS标准电池中的实现，以及为低功耗工作所做的优化。由此产生的核心在1.5ms内计算配对，功耗低于4mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A low-power pairing-based cryptographic accelerator for embedded security applications

We report on the implementation of an IP core for Pairing-based cryptography. The core performs an elliptic curve cryptographic operation called the Tate Pairing over the field GF(2251). In this paper, we describe the implementation of the design in TSMC 65nm GP CMOS standard cells and the optimisations made for low-power operation. The resulting core computes the pairing in 1.5ms and consumes less than 4mW.

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2009 IEEE International SOC Conference (SOCC)

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