{"title":"用户可配置的门阵列RAM编译器","authors":"R. L. Steinweg, M. Zampaglione, P. Lin","doi":"10.1109/ASIC.1989.123239","DOIUrl":null,"url":null,"abstract":"A flexible RAM compiler for gate arrays that is fully integrated into the user design tools is described. The various hardware and software features of the compiler are described, including variable aspect ratio with automatic selection, along with the design tool integration. The RAM compiled for minimum area came out with the 32 words in the core organized as 32 words down by one word across. It has a typical access time of about 10 ns. The RAM compiled for most square aspect ratio ended up with a core organization of 16 words down by 2 words across and an access time of about 8 ns. The RAM compiled for minimum access time has a core organization of 8 words down by 4 words across, and an access time of about 7 ns. If desired, other aspect ratio variations than those chosen automatically using the optimization criteria can be compiled by using the manual override option to specify the core organization directly.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A user-configurable RAM compiler for gate arrays\",\"authors\":\"R. L. Steinweg, M. Zampaglione, P. Lin\",\"doi\":\"10.1109/ASIC.1989.123239\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A flexible RAM compiler for gate arrays that is fully integrated into the user design tools is described. The various hardware and software features of the compiler are described, including variable aspect ratio with automatic selection, along with the design tool integration. The RAM compiled for minimum area came out with the 32 words in the core organized as 32 words down by one word across. It has a typical access time of about 10 ns. The RAM compiled for most square aspect ratio ended up with a core organization of 16 words down by 2 words across and an access time of about 8 ns. The RAM compiled for minimum access time has a core organization of 8 words down by 4 words across, and an access time of about 7 ns. If desired, other aspect ratio variations than those chosen automatically using the optimization criteria can be compiled by using the manual override option to specify the core organization directly.<<ETX>>\",\"PeriodicalId\":245997,\"journal\":{\"name\":\"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-09-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1989.123239\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1989.123239","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A flexible RAM compiler for gate arrays that is fully integrated into the user design tools is described. The various hardware and software features of the compiler are described, including variable aspect ratio with automatic selection, along with the design tool integration. The RAM compiled for minimum area came out with the 32 words in the core organized as 32 words down by one word across. It has a typical access time of about 10 ns. The RAM compiled for most square aspect ratio ended up with a core organization of 16 words down by 2 words across and an access time of about 8 ns. The RAM compiled for minimum access time has a core organization of 8 words down by 4 words across, and an access time of about 7 ns. If desired, other aspect ratio variations than those chosen automatically using the optimization criteria can be compiled by using the manual override option to specify the core organization directly.<>
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