W. El-Halwagy, A. Nag, P. Hisayasu, F. Aryanfar, P. Mousavi, M. Hossain
{"title":"用于5G移动通信的28GHz正交分数n合成器，在65nm CMOS中抖动小于100fs","authors":"W. El-Halwagy, A. Nag, P. Hisayasu, F. Aryanfar, P. Mousavi, M. Hossain","doi":"10.1109/RFIC.2016.7508265","DOIUrl":null,"url":null,"abstract":"A 26-32GHz quadrature cascaded phase locked loop (PLL) is presented. The PLL is implemented in 65nm bulk CMOS, consuming 27mW and has less than 100fsec integrated jitter with -114.4 and -112.6dBc/Hz phase noise at 1MHz offset for integer and fractional modes, respectively.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"A 28GHz quadrature fractional-N synthesizer for 5G mobile communication with less than 100fs jitter in 65nm CMOS\",\"authors\":\"W. El-Halwagy, A. Nag, P. Hisayasu, F. Aryanfar, P. Mousavi, M. Hossain\",\"doi\":\"10.1109/RFIC.2016.7508265\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 26-32GHz quadrature cascaded phase locked loop (PLL) is presented. The PLL is implemented in 65nm bulk CMOS, consuming 27mW and has less than 100fsec integrated jitter with -114.4 and -112.6dBc/Hz phase noise at 1MHz offset for integer and fractional modes, respectively.\",\"PeriodicalId\":163595,\"journal\":{\"name\":\"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-05-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RFIC.2016.7508265\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC.2016.7508265","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 28GHz quadrature fractional-N synthesizer for 5G mobile communication with less than 100fs jitter in 65nm CMOS
A 26-32GHz quadrature cascaded phase locked loop (PLL) is presented. The PLL is implemented in 65nm bulk CMOS, consuming 27mW and has less than 100fsec integrated jitter with -114.4 and -112.6dBc/Hz phase noise at 1MHz offset for integer and fractional modes, respectively.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
