Relibability assessment of wafer level chip scale package (WLCSP) based on distance-to-neutral point (DNP)

Wafer Level Chip Scale Package (WLCSP) is one of the most compact packages which provide good electrical and thermal performance depending on the reliability of the solder joint interconnections to the printed circuit board (PCB). Due to rapid advancements in integrated circuit (IC) fabrication, lower cost per die is achieved when the die count per wafer is high. With the number of IOs (input/output) per die increase which induces the die size and distance to neutral point also increases. Board-level reliability is always a main concern for WLCSP especially without underfill (UF). A common failure mechanism would be solder joint fatigue due to the coefficient of thermal expansion (CTE) mismatch. This would become worse by increasing the distance-to-neutral point (DNP). To improve the reliability, understanding of DNP limitation is necessary. In this paper, different wafer level package configurations are analysed through thermo-mechanical finite element method (FEM) simulation and validated with the thermal cyclic test.