RISP design using tightly coupled reconfigurable FPGA cores

Reconfigurable Instruction Set Processors are the next generation processors which can adapt their instruction sets through a reconfiguration process in their hardware according to the demand of the application being under execution on them. In this way the processors adapt the hardware which is the most suitable solution for the running application and hence it accelerates the performance gain. The reconfigurable instruction set processors are programmable processors that contain the reconfigurable logic in one or more of their functional units. Among the most important design parameters are: the granularity of the reconfigurable logic, the structure of the configuration memory, the instructions encoding formats and the types of instructions supported. In this research paper a reconfigurable instruction set processor design has been introduced by using the tightly coupled reconfigurable cores. The proposed design is capable of loading partial configurations at run-time without disturbing the execution of running application. The proposed processor supports the demand driven modification of its instruction set. Implemented with partially reconfigurable field programmable gate array cores like those provided by Xilinx corporation, the processor treats the instructions as removable modules that are paged in and paged out through the partial reconfiguration as is demanded by the running application.