Performance comparison of asymmetric drain/source topology in nanoscale Double Gate vertical MOSFET

Double Gate MOSFET structure is a promising architecture for advanced devices in nanometer regime. This paper elaborates the asymmetric topology of Vertical Double Gate MOSFET (VDGM) with ORI method as source/drain fabricating technique using numerical analysis approach. The electrical characteristics of the drain-on-top (DOT) and source-on-top (SOT) topology were analyzed, especially in the sub-threshold performance, to observe the short channel effect (SCE) of the device. The result shows that silicon pillar thickness reduction enhance the DIBL performance, while the threshold voltage roll-off change in nearly the same degree with the thickness variation. The floating body effect will likely occur for thicker silicon pillar in SOT, as the drain's depletion layer creates deeper barrier between substrate and pillar region. The performance comparison of sub-threshold slope revealed better SCE control for DOT topology in the lower silicon thickness for short channel length up to 30 nm.