{"title":"降低3D IC布线的温升","authors":"K. Pandiaraj, P. Sivakumar, N. Geetharamani","doi":"10.1109/ICEICE.2017.8191907","DOIUrl":null,"url":null,"abstract":"In Three Dimensional Integration Circuit (3D IC) challenges involved in removing heat from the intervening layers. Here, the thermal analysis of TTSVs (Thermal Through Silicon Vias) at the heat sink of the circuit and also the optimizations of corresponding heat sinks has been carried out using Genetic algorithm (GA) with IBM-route benchmark circuits as a inputs. Compared to the previous experimental results, the thermal aware between the routing layers in 3D IC has been reduced to a certain extent using this algorithmic approach. Our approach is achieves 7%.","PeriodicalId":110529,"journal":{"name":"2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Reduction of temperature rise in 3D IC routing\",\"authors\":\"K. Pandiaraj, P. Sivakumar, N. Geetharamani\",\"doi\":\"10.1109/ICEICE.2017.8191907\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In Three Dimensional Integration Circuit (3D IC) challenges involved in removing heat from the intervening layers. Here, the thermal analysis of TTSVs (Thermal Through Silicon Vias) at the heat sink of the circuit and also the optimizations of corresponding heat sinks has been carried out using Genetic algorithm (GA) with IBM-route benchmark circuits as a inputs. Compared to the previous experimental results, the thermal aware between the routing layers in 3D IC has been reduced to a certain extent using this algorithmic approach. Our approach is achieves 7%.\",\"PeriodicalId\":110529,\"journal\":{\"name\":\"2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE)\",\"volume\":\"2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICEICE.2017.8191907\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEICE.2017.8191907","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
摘要
在三维集成电路(3D IC)的挑战涉及到从中间层去除热量。本文以ibm路由基准电路为输入，采用遗传算法(GA)对电路散热器处的TTSVs (thermal Through Silicon Vias)进行了热分析，并对相应的散热器进行了优化。与以往的实验结果相比，该算法在一定程度上降低了三维集成电路中路由层之间的热感知。我们的目标是达到7%。
In Three Dimensional Integration Circuit (3D IC) challenges involved in removing heat from the intervening layers. Here, the thermal analysis of TTSVs (Thermal Through Silicon Vias) at the heat sink of the circuit and also the optimizations of corresponding heat sinks has been carried out using Genetic algorithm (GA) with IBM-route benchmark circuits as a inputs. Compared to the previous experimental results, the thermal aware between the routing layers in 3D IC has been reduced to a certain extent using this algorithmic approach. Our approach is achieves 7%.
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