Pub Date : 2017-12-14DOI: 10.1109/ICEICE.2017.8191877
G. Kanagachidambaresan, R. Anand, Akhtar Kalam
Maximum Power Point Tracking (MPPT) algorithm for different drives serving different application is the current interest of many researchers. In this paper a P & O (P&O) based MPPT controller is designed to investigate the performance of BLDC motor. Here Perturb and Observe (P&0) based MPPT controller with and without interleaved converter is compared. The proposed model and controller methodology provides reduced current and voltage ripple and promotes efficiency. The speed control of BLDC is also tested for its novel working under different load condition. The model is designed in Matlab Simulink to ensure its novel working and also compared with traditional Boost Converter (BC). The proposed model outperforms the traditional BC as per the claim made.
{"title":"Perturb and Observe (P&O) based MPPT controller for PV connected brushless DC motor drive","authors":"G. Kanagachidambaresan, R. Anand, Akhtar Kalam","doi":"10.1109/ICEICE.2017.8191877","DOIUrl":"https://doi.org/10.1109/ICEICE.2017.8191877","url":null,"abstract":"Maximum Power Point Tracking (MPPT) algorithm for different drives serving different application is the current interest of many researchers. In this paper a P & O (P&O) based MPPT controller is designed to investigate the performance of BLDC motor. Here Perturb and Observe (P&0) based MPPT controller with and without interleaved converter is compared. The proposed model and controller methodology provides reduced current and voltage ripple and promotes efficiency. The speed control of BLDC is also tested for its novel working under different load condition. The model is designed in Matlab Simulink to ensure its novel working and also compared with traditional Boost Converter (BC). The proposed model outperforms the traditional BC as per the claim made.","PeriodicalId":110529,"journal":{"name":"2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128872665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-04-27DOI: 10.1109/ICEICE.2017.8191846
R. Anand, G. R. Kanagachidambaresan, M. Balaji, K.S. Chandragupta Mauryan
Smart environment and Pervasive Computing has deeply influenced the present power system. The present smart grid is capable of determining and handling the load anywhere, anytime due to the Wireless communication. The Smart Meter (SM) is enabled with communication module, potential transformer and current transformer to measure the amount of power being used. A Zigbee communication enabled SM is designed for a smart grid and its performance is evaluated in this paper. The data error rate is also evaluated.
{"title":"Design of smart meter for smart grid application through true time — MATLAB","authors":"R. Anand, G. R. Kanagachidambaresan, M. Balaji, K.S. Chandragupta Mauryan","doi":"10.1109/ICEICE.2017.8191846","DOIUrl":"https://doi.org/10.1109/ICEICE.2017.8191846","url":null,"abstract":"Smart environment and Pervasive Computing has deeply influenced the present power system. The present smart grid is capable of determining and handling the load anywhere, anytime due to the Wireless communication. The Smart Meter (SM) is enabled with communication module, potential transformer and current transformer to measure the amount of power being used. A Zigbee communication enabled SM is designed for a smart grid and its performance is evaluated in this paper. The data error rate is also evaluated.","PeriodicalId":110529,"journal":{"name":"2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122534527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-04-27DOI: 10.1109/ICEICE.2017.8191959
S. Swamynathan, V. Banumathi
An Arithmetic logic Unit (ALU) is used in arithmetic, logical function in all processor. It is also an important subsystem in digital system design. Arithmetic Logic Unit (ALU) is one of the most important components of any system and is used in many appliances like calculators, cell phones, and computers. A 32-bit ALU was designed using Verilog HDL with the logical gates such as AND and OR for each one bit ALU circuit. The design was implemented in Xilinx. It can work fast than the ALU processor using less power. The design of an ALU and a Cache memory for use in a high performance processor was examined. Reversible logic vital in recent years because it has ability to reduce the power dissipation which is main requirement in low power design. ALU which are designed using non reversible logic gates consume more power. So there is a need for lesser power consumption and the reversible logic has been playing vital role during recent years for low power VLSI Design techniques. This technique helps in reducing power consumption and power dissipation. This paper presents an implementation of ALU based on reversible logic while comparing it to an ALU architecture with the normal logic gates. All the modules are simulated in modelsim SE 6.4c and synthesised using Xilinx ISE 14.5. ALU which is designed using non reversible logic gates consume more power of about 0.312 mw and the implementation of ALU based on reversible logic reduces the power consumption during operations to about 5.1 percentages.
算术逻辑单元(ALU)用于所有处理器的算术、逻辑功能。它也是数字系统设计中的一个重要子系统。算术逻辑单元(ALU)是任何系统中最重要的组件之一，用于许多设备，如计算器、手机和计算机。采用Verilog HDL语言设计了一个32位ALU电路，并为每个位ALU电路设置与、或等逻辑门。该设计在Xilinx中实现。它比ALU处理器工作速度快，功耗更低。研究了用于高性能处理器的ALU和Cache的设计。可逆逻辑由于具有降低功耗的能力，是低功耗设计的主要要求，近年来受到广泛关注。使用非可逆逻辑门设计的ALU消耗更多的功率。因此，需要更低的功耗，可逆逻辑近年来在低功耗VLSI设计技术中发挥着至关重要的作用。这种技术有助于降低功耗和功耗。本文提出了一种基于可逆逻辑的ALU的实现方法，并将其与具有普通逻辑门的ALU结构进行了比较。所有模块均在modelsim SE 6.4c中进行仿真，并使用Xilinx ISE 14.5进行合成。采用不可逆逻辑门设计的ALU的功耗约为0.312 mw，基于可逆逻辑的ALU的实现将运行期间的功耗降低了约5.1个百分点。
{"title":"Design and analysis of FPGA based 32 bit ALU using reversible gates","authors":"S. Swamynathan, V. Banumathi","doi":"10.1109/ICEICE.2017.8191959","DOIUrl":"https://doi.org/10.1109/ICEICE.2017.8191959","url":null,"abstract":"An Arithmetic logic Unit (ALU) is used in arithmetic, logical function in all processor. It is also an important subsystem in digital system design. Arithmetic Logic Unit (ALU) is one of the most important components of any system and is used in many appliances like calculators, cell phones, and computers. A 32-bit ALU was designed using Verilog HDL with the logical gates such as AND and OR for each one bit ALU circuit. The design was implemented in Xilinx. It can work fast than the ALU processor using less power. The design of an ALU and a Cache memory for use in a high performance processor was examined. Reversible logic vital in recent years because it has ability to reduce the power dissipation which is main requirement in low power design. ALU which are designed using non reversible logic gates consume more power. So there is a need for lesser power consumption and the reversible logic has been playing vital role during recent years for low power VLSI Design techniques. This technique helps in reducing power consumption and power dissipation. This paper presents an implementation of ALU based on reversible logic while comparing it to an ALU architecture with the normal logic gates. All the modules are simulated in modelsim SE 6.4c and synthesised using Xilinx ISE 14.5. ALU which is designed using non reversible logic gates consume more power of about 0.312 mw and the implementation of ALU based on reversible logic reduces the power consumption during operations to about 5.1 percentages.","PeriodicalId":110529,"journal":{"name":"2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE)","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124584175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-04-27DOI: 10.1109/ICEICE.2017.8192446
P. Sivakumar, G. Karthy, K. V. Bharani
An efficient BISR technique is proposed to find an optimum point of performance scheme is proposed for 2D and 3D memories. Fault Tolerant Improvement Mechanism is provided for all memories using Built-In Self-Test (March Test Algorithm) which figure out the memory faults, total number of faults, and irreparability and test the memories simultaneously. Using LFSR architecture the transistor is reduced. After all memories are tested, only faulty memories are sequentially tested and the shared BIRA repaired the fault according to the sizes of memories in descending order to obtain the fast test and repair with low area overhead. Circuit design is created using LFSR architecture that reduces the flipflop level which leads to reduce the time. The detected faults are send to the BIST, then the BIST sends the faults to the BIRA module which uses Cresta for repair analysis and sends the solution. Three number of spare rows & columns are added along with 2 sub analyzers are used to accomplish a fast analysis speed, and an optimal repair rate for every different possible combinations of spare rows & columns.
提出了一种有效的BISR技术来寻找二维和三维存储器的最佳性能点。采用内置自检(March Test Algorithm)算法，对所有内存提供容错改进机制，对内存故障、故障总数、不可恢复性进行检测，同时对内存进行测试。采用LFSR结构减小了晶体管的损耗。在对所有内存进行测试后，只对有故障的内存进行顺序测试，共享BIRA按照内存大小由大到小的顺序进行故障修复，以获得低面积开销的快速测试和修复。电路设计采用LFSR架构，减少触发器电平，从而减少时间。检测到的故障被发送到BIST，然后BIST将故障发送到BIRA模块，BIRA模块使用Cresta进行修复分析并发送解决方案。三个数量的备用行和列与2子分析仪一起添加，以实现快速的分析速度，并为备用行和列的每一个不同的可能组合的最佳修复率。
{"title":"Fault tolerant improvement mechanism for 3D memories using built-in self repair scheme","authors":"P. Sivakumar, G. Karthy, K. V. Bharani","doi":"10.1109/ICEICE.2017.8192446","DOIUrl":"https://doi.org/10.1109/ICEICE.2017.8192446","url":null,"abstract":"An efficient BISR technique is proposed to find an optimum point of performance scheme is proposed for 2D and 3D memories. Fault Tolerant Improvement Mechanism is provided for all memories using Built-In Self-Test (March Test Algorithm) which figure out the memory faults, total number of faults, and irreparability and test the memories simultaneously. Using LFSR architecture the transistor is reduced. After all memories are tested, only faulty memories are sequentially tested and the shared BIRA repaired the fault according to the sizes of memories in descending order to obtain the fast test and repair with low area overhead. Circuit design is created using LFSR architecture that reduces the flipflop level which leads to reduce the time. The detected faults are send to the BIST, then the BIST sends the faults to the BIRA module which uses Cresta for repair analysis and sends the solution. Three number of spare rows & columns are added along with 2 sub analyzers are used to accomplish a fast analysis speed, and an optimal repair rate for every different possible combinations of spare rows & columns.","PeriodicalId":110529,"journal":{"name":"2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125556822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-04-01DOI: 10.1109/ICEICE.2017.8191951
T. Srikanth, S. Selvi, V. Pushya
Power system is nothing but a power Generation, power Transmission and power Distribution. Most of the conventional energy sources generate the power at the hill areas or at the longer distances from electrical consumers, so that an electrical transmission and distribution system plays a vital role in power system. Since most of the electrical loads are inductive loads and transmission and distribution lines itself not pure resistive lines, there is a reactive power requirement in the transmission and distribution systems. If transmission and distribution lines are not maintaining the required reactive power limits, then power losses increase and it also effect on the stability. There are different types of sources available for reactive power management in the power system are shunt capacitors, synchronous condensers and Static Var compensator (SVC). In this paper, optimal placement of SVC in transmission and distribution lines along with Distributed Generation sources (DGS) is analyzed based on better reactive support and stability limits in the lines.
{"title":"Optimal placement of static VAR compensator (SVC) in power system along with wind power generation","authors":"T. Srikanth, S. Selvi, V. Pushya","doi":"10.1109/ICEICE.2017.8191951","DOIUrl":"https://doi.org/10.1109/ICEICE.2017.8191951","url":null,"abstract":"Power system is nothing but a power Generation, power Transmission and power Distribution. Most of the conventional energy sources generate the power at the hill areas or at the longer distances from electrical consumers, so that an electrical transmission and distribution system plays a vital role in power system. Since most of the electrical loads are inductive loads and transmission and distribution lines itself not pure resistive lines, there is a reactive power requirement in the transmission and distribution systems. If transmission and distribution lines are not maintaining the required reactive power limits, then power losses increase and it also effect on the stability. There are different types of sources available for reactive power management in the power system are shunt capacitors, synchronous condensers and Static Var compensator (SVC). In this paper, optimal placement of SVC in transmission and distribution lines along with Distributed Generation sources (DGS) is analyzed based on better reactive support and stability limits in the lines.","PeriodicalId":110529,"journal":{"name":"2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115445401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-04-01DOI: 10.1109/ICEICE.2017.8191874
D. Bell, D. Asir
This paper proposes a congestion control technique for intermittent networks (ICNs), it is a class of mobile ad hoc networks where there does not exist a complete end-to-end path between source and destination. The routing algorithm used is Self Adaptive Utility based Routing Protocol (SAURP) that makes the network self adaptable to the network behavior. Nodes often get congested with too many messages to store and carry. Congestion control in ICNs does not rely on end-end ACK. Congestion here we refer to node/storage congestion. Buffer information is updated in the routing messages. Experimental results through simulation show that this technique improves delivery ratio and delay.
本文提出了一种针对间歇网络(ICNs)的拥塞控制技术，间歇网络是一类在源和目的之间不存在完整的端到端路径的移动自组织网络。使用的路由算法是基于自适应实用程序的路由协议SAURP (Self Adaptive Utility based routing Protocol)，使网络能够自适应网络行为。节点通常会因为需要存储和传输的消息太多而变得拥挤。ICNs中的拥塞控制不依赖于端到端ACK。这里我们指的是节点/存储拥塞。缓冲区信息在路由消息中更新。仿真实验结果表明，该技术提高了传输率和延迟。
{"title":"Autonomous congestion control deploying SAURP","authors":"D. Bell, D. Asir","doi":"10.1109/ICEICE.2017.8191874","DOIUrl":"https://doi.org/10.1109/ICEICE.2017.8191874","url":null,"abstract":"This paper proposes a congestion control technique for intermittent networks (ICNs), it is a class of mobile ad hoc networks where there does not exist a complete end-to-end path between source and destination. The routing algorithm used is Self Adaptive Utility based Routing Protocol (SAURP) that makes the network self adaptable to the network behavior. Nodes often get congested with too many messages to store and carry. Congestion control in ICNs does not rely on end-end ACK. Congestion here we refer to node/storage congestion. Buffer information is updated in the routing messages. Experimental results through simulation show that this technique improves delivery ratio and delay.","PeriodicalId":110529,"journal":{"name":"2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122796333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-04-01DOI: 10.1109/ICEICE.2017.8192445
Vidushi Mahalwar, Y. Choukiker
In this paper, the probe position effects on efficiency of mode excitation, radiation pattern and null steering has been studied. The radiation patterns for different combinations of the mode have been obtained here. It has been observed that the radiation patterns has two nulls which can be steered independently and is required in many applications such as antijamming antennas. The radiation pattern reconfiguration is achieved by exciting the dominant TM11 mode along with the higher order TM21 and TM31 modes. It is found that the symmetry of the radiation pattern can be improved by the finite ground plane.
{"title":"Study of radiation patterns of circular patch antenna at different modes","authors":"Vidushi Mahalwar, Y. Choukiker","doi":"10.1109/ICEICE.2017.8192445","DOIUrl":"https://doi.org/10.1109/ICEICE.2017.8192445","url":null,"abstract":"In this paper, the probe position effects on efficiency of mode excitation, radiation pattern and null steering has been studied. The radiation patterns for different combinations of the mode have been obtained here. It has been observed that the radiation patterns has two nulls which can be steered independently and is required in many applications such as antijamming antennas. The radiation pattern reconfiguration is achieved by exciting the dominant TM11 mode along with the higher order TM21 and TM31 modes. It is found that the symmetry of the radiation pattern can be improved by the finite ground plane.","PeriodicalId":110529,"journal":{"name":"2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114283282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-04-01DOI: 10.1109/ICEICE.2017.8191867
T. E. Santhia, R. Bharathi, M. Revathy
Scaling of CMOS technology to nanoscale increases soft error rate in memory cells. Both single bit upset and Multiple Cell Upsets (MCUs) causes reliability issues in memory applications. Transient multiple cell upsets (MCUs) are becoming major issues in the reliability of memories exposed to radiation environment and affect large number of cells. Hence to provide fault tolerant memory cells, Error detection and Correction Codes are used which are being discussed here in this paper.
{"title":"Error detection and correction using decimal matrix code: Survey","authors":"T. E. Santhia, R. Bharathi, M. Revathy","doi":"10.1109/ICEICE.2017.8191867","DOIUrl":"https://doi.org/10.1109/ICEICE.2017.8191867","url":null,"abstract":"Scaling of CMOS technology to nanoscale increases soft error rate in memory cells. Both single bit upset and Multiple Cell Upsets (MCUs) causes reliability issues in memory applications. Transient multiple cell upsets (MCUs) are becoming major issues in the reliability of memories exposed to radiation environment and affect large number of cells. Hence to provide fault tolerant memory cells, Error detection and Correction Codes are used which are being discussed here in this paper.","PeriodicalId":110529,"journal":{"name":"2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE)","volume":"286 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114386610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-04-01DOI: 10.1109/ICEICE.2017.8191841
Abhishek Pandiya, Y. Choukiker
In this paper, Theory of Characteristic Mode (TCM) has been exploited to enhance the performance of MIMO antenna. Characteristic modes of Chassis has been analyzed, it has been observed that only one mode is resonating around 1GHz. To enable more than one characteristic mode to resonate around 1GHz, Two metal strips are attached along the length of the chassis with the help of shorting pins. A new characteristic mode has been enabled at about 900 MHz due to this modification. In order to obtain characteristic mode at further lower frequency, the newly attached metal strip is meandered. A shift in the characteristic mode has been observed due to this. Afterwards, Dual antenna design is proposed. The Dual antenna consists of metal strip antenna and coupled antenna. The feeding method is proposed with the help of theory of characteristic mode (TCM) to excite the antenna chassis mode and metal strip mode efficiently. The results shows that the strip antenna covers 849–953MHz (LTE Band8) and chassis mode antenna covers frequency 950–1120 MHz.
{"title":"Characteristic mode analysis of mobile hand held device for MIMO applications","authors":"Abhishek Pandiya, Y. Choukiker","doi":"10.1109/ICEICE.2017.8191841","DOIUrl":"https://doi.org/10.1109/ICEICE.2017.8191841","url":null,"abstract":"In this paper, Theory of Characteristic Mode (TCM) has been exploited to enhance the performance of MIMO antenna. Characteristic modes of Chassis has been analyzed, it has been observed that only one mode is resonating around 1GHz. To enable more than one characteristic mode to resonate around 1GHz, Two metal strips are attached along the length of the chassis with the help of shorting pins. A new characteristic mode has been enabled at about 900 MHz due to this modification. In order to obtain characteristic mode at further lower frequency, the newly attached metal strip is meandered. A shift in the characteristic mode has been observed due to this. Afterwards, Dual antenna design is proposed. The Dual antenna consists of metal strip antenna and coupled antenna. The feeding method is proposed with the help of theory of characteristic mode (TCM) to excite the antenna chassis mode and metal strip mode efficiently. The results shows that the strip antenna covers 849–953MHz (LTE Band8) and chassis mode antenna covers frequency 950–1120 MHz.","PeriodicalId":110529,"journal":{"name":"2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128640613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-04-01DOI: 10.1109/ICEICE.2017.8191878
Kantilal Dayalal Joshi, V. Chandrakar
This paper demonstrates the utility of Ultracapacitor as value addition to the D.C. link of Voltage source converter based FACTS controllers. This has been shown using a 500kV transmission system with three types of devices viz. STATCOM, SSSC and UPFC. A full-scale non linear model of all three devices with 48 pulse configuration is used. Firstly the system is checked under normal operating conditions. Next, the control strategy for control of ultracapacitor in coordination with power oscillations is derived. Then sizing of ultracapacitor bank for integration is done. Finally, a comparative study is carried out for all three types of devices with reference to power oscillation damping improvement.
{"title":"Power oscillation damping using ultracapcitor and voltage source based FACTS controllers","authors":"Kantilal Dayalal Joshi, V. Chandrakar","doi":"10.1109/ICEICE.2017.8191878","DOIUrl":"https://doi.org/10.1109/ICEICE.2017.8191878","url":null,"abstract":"This paper demonstrates the utility of Ultracapacitor as value addition to the D.C. link of Voltage source converter based FACTS controllers. This has been shown using a 500kV transmission system with three types of devices viz. STATCOM, SSSC and UPFC. A full-scale non linear model of all three devices with 48 pulse configuration is used. Firstly the system is checked under normal operating conditions. Next, the control strategy for control of ultracapacitor in coordination with power oscillations is derived. Then sizing of ultracapacitor bank for integration is done. Finally, a comparative study is carried out for all three types of devices with reference to power oscillation damping improvement.","PeriodicalId":110529,"journal":{"name":"2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126389154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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