{"title":"基于阴影匹配线电压检测的凸轮失匹配低功耗检测技术","authors":"Jianwei Zhang, Y. Ye, Bin-Da Liu","doi":"10.1145/1165573.1165605","DOIUrl":null,"url":null,"abstract":"A new mismatch-dependent low-power technique is presented for content-addressable memories (CAMs). With a novel shadow match-line voltage-detecting scheme, the word circuits realize fast self-disable of the charging paths in case of mismatches. Since the majority of CAMs words are mismatched, a significant power is reduced with a high search speed. Simulation results show the proposed 256-word times 144-bit ternary CAM, using 0.13-mum 1.2-V CMOS process, achieves 0.51 fJ/bit/search for the word circuit with less than 900 ps search time. The achievement illustrates a 77% energy-delay-product (EDP) reduction as compared to the speed-optimized current-saving scheme","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"A New Mismatch-Dependent Low Power Technique with Shadow Match-Line Voltage-Detecting Scheme for CAMs\",\"authors\":\"Jianwei Zhang, Y. Ye, Bin-Da Liu\",\"doi\":\"10.1145/1165573.1165605\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new mismatch-dependent low-power technique is presented for content-addressable memories (CAMs). With a novel shadow match-line voltage-detecting scheme, the word circuits realize fast self-disable of the charging paths in case of mismatches. Since the majority of CAMs words are mismatched, a significant power is reduced with a high search speed. Simulation results show the proposed 256-word times 144-bit ternary CAM, using 0.13-mum 1.2-V CMOS process, achieves 0.51 fJ/bit/search for the word circuit with less than 900 ps search time. The achievement illustrates a 77% energy-delay-product (EDP) reduction as compared to the speed-optimized current-saving scheme\",\"PeriodicalId\":119229,\"journal\":{\"name\":\"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-10-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/1165573.1165605\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1165573.1165605","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
摘要
提出了一种新的基于失匹配的低功耗内容寻址存储器技术。该电路采用了一种新颖的阴影匹配线电压检测方案,实现了充电路径在不匹配情况下的快速自禁用。由于大多数CAMs单词是不匹配的,因此在高搜索速度的同时显著降低了功率。仿真结果表明,采用0.13 μ m 1.2 v CMOS工艺的256字144位三元制CAM,在小于900 ps的搜索时间下,实现了字电路的0.51 fJ/bit/搜索。这一成果表明,与速度优化的节电方案相比,能量延迟积(EDP)降低了77%
A New Mismatch-Dependent Low Power Technique with Shadow Match-Line Voltage-Detecting Scheme for CAMs
A new mismatch-dependent low-power technique is presented for content-addressable memories (CAMs). With a novel shadow match-line voltage-detecting scheme, the word circuits realize fast self-disable of the charging paths in case of mismatches. Since the majority of CAMs words are mismatched, a significant power is reduced with a high search speed. Simulation results show the proposed 256-word times 144-bit ternary CAM, using 0.13-mum 1.2-V CMOS process, achieves 0.51 fJ/bit/search for the word circuit with less than 900 ps search time. The achievement illustrates a 77% energy-delay-product (EDP) reduction as compared to the speed-optimized current-saving scheme