Kun Mao, M. Qiao, Lingli Jiang, Huaping Jiang, Zehong Li, Weizhong Chen, Zhaoji Li, Bo Zhang
{"title":"一种0.35 μm 700 V BCD技术，具有自隔离和非隔离超低比导通电阻DB-nLDMOS","authors":"Kun Mao, M. Qiao, Lingli Jiang, Huaping Jiang, Zehong Li, Weizhong Chen, Zhaoji Li, Bo Zhang","doi":"10.1109/ISPSD.2013.6694429","DOIUrl":null,"url":null,"abstract":"Integrated in a 0.35 μm 700 V BCD process platform, ultra-low R<sub>on, sp</sub> 700 V self-ISO (isolated) and NISO (non-isolated) DB-nLDMOS (dual P-buried-layer nLDMOS) are proposed in this paper. 800 V and 780 V are achieved for NISO and ISO DB-nLDMOS, of which R<sub>on, sp</sub> are 11.5 Ω·mm<sup>2</sup> and 11.2 Ω·mm<sup>2</sup>, respectively. Utra-low R<sub>on, sp</sub> benefits from optimized device size and strict limitations for annealing temperature and time after P-bury-layer implantation. For ISO DB-nLDMOS, by separately implanting NWELLs, NWELL drift region of low doping concentration under gate poly is achieved and then premature avalanche breakdown around bird's beak is avoided. Moreover, a 600 V DB-nJFET (dual P-buried-layer nJFET) with innovative 3D pinch-off structure is also presented.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"30","resultStr":"{\"title\":\"A 0.35 μm 700 V BCD technology with self-isolated and non-isolated ultra-low specific on-resistance DB-nLDMOS\",\"authors\":\"Kun Mao, M. Qiao, Lingli Jiang, Huaping Jiang, Zehong Li, Weizhong Chen, Zhaoji Li, Bo Zhang\",\"doi\":\"10.1109/ISPSD.2013.6694429\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Integrated in a 0.35 μm 700 V BCD process platform, ultra-low R<sub>on, sp</sub> 700 V self-ISO (isolated) and NISO (non-isolated) DB-nLDMOS (dual P-buried-layer nLDMOS) are proposed in this paper. 800 V and 780 V are achieved for NISO and ISO DB-nLDMOS, of which R<sub>on, sp</sub> are 11.5 Ω·mm<sup>2</sup> and 11.2 Ω·mm<sup>2</sup>, respectively. Utra-low R<sub>on, sp</sub> benefits from optimized device size and strict limitations for annealing temperature and time after P-bury-layer implantation. For ISO DB-nLDMOS, by separately implanting NWELLs, NWELL drift region of low doping concentration under gate poly is achieved and then premature avalanche breakdown around bird's beak is avoided. Moreover, a 600 V DB-nJFET (dual P-buried-layer nJFET) with innovative 3D pinch-off structure is also presented.\",\"PeriodicalId\":175520,\"journal\":{\"name\":\"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-05-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"30\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPSD.2013.6694429\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.2013.6694429","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 30
摘要
在0.35 μm 700 V BCD工艺平台上集成了超低Ron、sp 700 V自iso(隔离)和NISO(非隔离)DB-nLDMOS(双p埋层nLDMOS)。NISO和ISO DB-nLDMOS的电压分别为800 V和780 V，其中Ron, sp分别为11.5 Ω·mm2和11.2 Ω·mm2。超低Ron, sp得益于优化的器件尺寸和p -埋层植入后对退火温度和时间的严格限制。对于ISO DB-nLDMOS，通过单独植入NWELL，实现栅聚下低掺杂浓度的NWELL漂移区，避免了鸟喙周围过早的雪崩击穿。此外，还提出了一种新颖的具有三维掐断结构的600 V DB-nJFET(双p埋层nJFET)。
A 0.35 μm 700 V BCD technology with self-isolated and non-isolated ultra-low specific on-resistance DB-nLDMOS
Integrated in a 0.35 μm 700 V BCD process platform, ultra-low Ron, sp 700 V self-ISO (isolated) and NISO (non-isolated) DB-nLDMOS (dual P-buried-layer nLDMOS) are proposed in this paper. 800 V and 780 V are achieved for NISO and ISO DB-nLDMOS, of which Ron, sp are 11.5 Ω·mm2 and 11.2 Ω·mm2, respectively. Utra-low Ron, sp benefits from optimized device size and strict limitations for annealing temperature and time after P-bury-layer implantation. For ISO DB-nLDMOS, by separately implanting NWELLs, NWELL drift region of low doping concentration under gate poly is achieved and then premature avalanche breakdown around bird's beak is avoided. Moreover, a 600 V DB-nJFET (dual P-buried-layer nJFET) with innovative 3D pinch-off structure is also presented.
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