{"title":"十进制部分积生成体系结构","authors":"I. D. Castellanos, J. Stine","doi":"10.1109/MWSCAS.2008.4616961","DOIUrl":null,"url":null,"abstract":"Interest in decimal arithmetic is growing considerably due to its relevance in financial and commercial applications. Previous developments on decimal multiplication focused on sequential implementations due to its complexity. However, recent studies have proposed parallel multipliers to improve performance. This paper clarifies recent techniques for partial product generation and presents implementation results and comparison of available partial product generation architectures. As opposed to previous implementations, which only propose partial product generation designs on paper, this research implements and expands each proposed architecture and addresses its utilization within decimal architectures.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Decimal partial product generation architectures\",\"authors\":\"I. D. Castellanos, J. Stine\",\"doi\":\"10.1109/MWSCAS.2008.4616961\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Interest in decimal arithmetic is growing considerably due to its relevance in financial and commercial applications. Previous developments on decimal multiplication focused on sequential implementations due to its complexity. However, recent studies have proposed parallel multipliers to improve performance. This paper clarifies recent techniques for partial product generation and presents implementation results and comparison of available partial product generation architectures. As opposed to previous implementations, which only propose partial product generation designs on paper, this research implements and expands each proposed architecture and addresses its utilization within decimal architectures.\",\"PeriodicalId\":118637,\"journal\":{\"name\":\"2008 51st Midwest Symposium on Circuits and Systems\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-09-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 51st Midwest Symposium on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2008.4616961\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 51st Midwest Symposium on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2008.4616961","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Interest in decimal arithmetic is growing considerably due to its relevance in financial and commercial applications. Previous developments on decimal multiplication focused on sequential implementations due to its complexity. However, recent studies have proposed parallel multipliers to improve performance. This paper clarifies recent techniques for partial product generation and presents implementation results and comparison of available partial product generation architectures. As opposed to previous implementations, which only propose partial product generation designs on paper, this research implements and expands each proposed architecture and addresses its utilization within decimal architectures.