亚阈值逻辑的鲁棒电平变换器设计

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI:10.1145/1165573.1165579

I. Chang, Jae-Joon Kim, K. Roy

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引用次数: 31

摘要

亚阈值核心逻辑和I/O之间的大电压差使得信号从核心电路转换到I/O电路极具挑战性。本文提出了时钟同步器和减摆幅逆变器两种新颖的电路来设计亚阈值逻辑的动态电平变换器和静态电平变换器。电路仿真表明，我们的电平变换器工作频率为> 500kHz，在20°c和40°c之间，电源电压为0.25V

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Robust Level Converter Design for Sub-threshold Logic

The large supply voltage difference between sub-threshold core logic and I/O makes it extremely challenging to convert signals from core circuit to I/O circuit. In this paper, we propose two novel circuits, clock synchronizer and reduced swing inverter to design dynamic and static level converters for sub-threshold logic. Circuit simulations shows that our level converters work at frequency > 500kHz between 20degC and 40degC with a supply voltage of 0.25V

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ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design

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