DPL thermal model of test microchip structure without cavity dedicated to estimation of nanoelectronic circuits thermal properties

This paper presents the comparison of the temperature distribution in the test structure chip obtained using Fourier-Kirchhoff and Dual-Phase-Lag heat transfer models. The investigated test structure consisting of two polysilicon resistors used as the heater and thermometer, which are located inside the silicon dioxide layer. The simulation results are compared with those which have been received using similar test structure containing two platinum resistors. Some numerical problems observed during the simulation of Dual-Phase-Lag heat transfer model have been also briefly presented.