{"title":"模拟集成电路分层布局设计中的多级网表划分方法","authors":"P. B. Wu, R. Mack, R. Massara","doi":"10.1109/MWSCAS.2000.951601","DOIUrl":null,"url":null,"abstract":"An algorithmic netlist partitioning approach for the hierarchical design of analog layout is presented. In addition to considering routability, partitioning operates under analog performance and area efficiency constraints. The multi-level partitioner is embedded with built-in move operators to enable designers to balance quality and design time. The effectiveness of the approach is shown by example results.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A multi-level netlist partitioning approach to hierarchical layout design of analog ICs\",\"authors\":\"P. B. Wu, R. Mack, R. Massara\",\"doi\":\"10.1109/MWSCAS.2000.951601\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An algorithmic netlist partitioning approach for the hierarchical design of analog layout is presented. In addition to considering routability, partitioning operates under analog performance and area efficiency constraints. The multi-level partitioner is embedded with built-in move operators to enable designers to balance quality and design time. The effectiveness of the approach is shown by example results.\",\"PeriodicalId\":437349,\"journal\":{\"name\":\"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)\",\"volume\":\"40 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-08-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2000.951601\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2000.951601","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A multi-level netlist partitioning approach to hierarchical layout design of analog ICs
An algorithmic netlist partitioning approach for the hierarchical design of analog layout is presented. In addition to considering routability, partitioning operates under analog performance and area efficiency constraints. The multi-level partitioner is embedded with built-in move operators to enable designers to balance quality and design time. The effectiveness of the approach is shown by example results.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
