未来星载系统基于机载fpga的SAR处理

Proceedings of the 2004 IEEE Radar Conference (IEEE Cat. No.04CH37509) Pub Date : 2004-04-26 DOI:10.1109/NRC.2004.1316388

C. Le, S. Chan, F. Cheng, W. Fang, M. Fischman, S. Hensley, R. Johnson, M. Jourdan, M. Marina, B. Parham, F. Rogez, P. Rosen, B. Shah, S. Taft

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引用次数: 40

摘要

我们提出了一种基于fpga的实时高性能容错硬件架构，用于未来星载系统中合成孔径雷达(SAR)图像的处理。特别地，我们讨论了集成设计方法，从顶层算法规范和系统需求，设计方法，功能验证和性能验证，到硬件设计和实现。

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Onboard FPGA-based SAR processing for future spaceborne systems

We present a real-time high-performance and fault-tolerant FPGA-based hardware architecture for the processing of synthetic aperture radar (SAR) images in future spaceborne systems. In particular, we discuss the integrated design approach, from top-level algorithm specifications and system requirements, design methodology, functional verification and performance validation, down to hardware design and implementation.

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Proceedings of the 2004 IEEE Radar Conference (IEEE Cat. No.04CH37509)

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