{"title":"采用片上测试芯片,最大限度地提高28nm零件的参数良率","authors":"J. Mueller, S. Jallepalli, R. Mooraka, S. Hector","doi":"10.1109/ICMTS.2015.7106107","DOIUrl":null,"url":null,"abstract":"We show that a well designed suite of process observation structures (POSt) that can be tested on a standard production tester is a valuable asset for achieving high parametric yields. Our ability to tailor test coverage and conditions based on circuit yield signatures has allowed us to obtain the needed learning within a small test time budget.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Employing an on-die test chip for maximizing parametric yields of 28nm parts\",\"authors\":\"J. Mueller, S. Jallepalli, R. Mooraka, S. Hector\",\"doi\":\"10.1109/ICMTS.2015.7106107\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We show that a well designed suite of process observation structures (POSt) that can be tested on a standard production tester is a valuable asset for achieving high parametric yields. Our ability to tailor test coverage and conditions based on circuit yield signatures has allowed us to obtain the needed learning within a small test time budget.\",\"PeriodicalId\":177627,\"journal\":{\"name\":\"Proceedings of the 2015 International Conference on Microelectronic Test Structures\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-03-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 2015 International Conference on Microelectronic Test Structures\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICMTS.2015.7106107\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMTS.2015.7106107","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Employing an on-die test chip for maximizing parametric yields of 28nm parts
We show that a well designed suite of process observation structures (POSt) that can be tested on a standard production tester is a valuable asset for achieving high parametric yields. Our ability to tailor test coverage and conditions based on circuit yield signatures has allowed us to obtain the needed learning within a small test time budget.