基于无监督学习的硬件木马自动检测:以FPGA为例

Shailesh Rajput, Jaya Dofe, Wafi Danesh
{"title":"基于无监督学习的硬件木马自动检测:以FPGA为例","authors":"Shailesh Rajput, Jaya Dofe, Wafi Danesh","doi":"10.1109/ISQED57927.2023.10129335","DOIUrl":null,"url":null,"abstract":"Field programmable gate arrays (FPGAs) are widely used in critical applications such as industrial, medical, automotive, and military systems due to their ability to be dynamically reconfigured at runtime. However, this reconfigurability also presents security concerns, as FPGA designs are encoded in a bitstream that adversaries can target for design cloning, IP theft, or hardware Trojan insertion. This work presents a proof-of-concept for detecting hardware Trojans (HT) in FPGA using an unsupervised machine-learning method that eliminates the need for reference models of HT. The proposed method is based on transforming the configuration bitstream into an encoded vector, bypassing the need for netlist reconstruction and allowing for HT detection based solely on the extracted FPGA layout information. Our method was evaluated against various HT attack scenarios and accurately detected all infected bitstreams.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Automating Hardware Trojan Detection Using Unsupervised Learning: A Case Study of FPGA\",\"authors\":\"Shailesh Rajput, Jaya Dofe, Wafi Danesh\",\"doi\":\"10.1109/ISQED57927.2023.10129335\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Field programmable gate arrays (FPGAs) are widely used in critical applications such as industrial, medical, automotive, and military systems due to their ability to be dynamically reconfigured at runtime. However, this reconfigurability also presents security concerns, as FPGA designs are encoded in a bitstream that adversaries can target for design cloning, IP theft, or hardware Trojan insertion. This work presents a proof-of-concept for detecting hardware Trojans (HT) in FPGA using an unsupervised machine-learning method that eliminates the need for reference models of HT. The proposed method is based on transforming the configuration bitstream into an encoded vector, bypassing the need for netlist reconstruction and allowing for HT detection based solely on the extracted FPGA layout information. Our method was evaluated against various HT attack scenarios and accurately detected all infected bitstreams.\",\"PeriodicalId\":315053,\"journal\":{\"name\":\"2023 24th International Symposium on Quality Electronic Design (ISQED)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-04-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2023 24th International Symposium on Quality Electronic Design (ISQED)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISQED57927.2023.10129335\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 24th International Symposium on Quality Electronic Design (ISQED)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED57927.2023.10129335","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

现场可编程门阵列(fpga)广泛应用于工业、医疗、汽车和军事系统等关键应用,因为它们能够在运行时动态重新配置。然而,这种可重构性也带来了安全问题,因为FPGA设计是用比特流编码的,攻击者可以针对比特流进行设计克隆、IP窃取或硬件木马插入。这项工作提出了一种使用无监督机器学习方法检测FPGA中的硬件木马(HT)的概念验证,该方法消除了对HT参考模型的需要。所提出的方法是基于将配置比特流转换为编码矢量,绕过网表重构的需要,并允许仅基于提取的FPGA布局信息进行HT检测。我们的方法针对各种HT攻击场景进行了评估,并准确检测到所有受感染的比特流。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
Automating Hardware Trojan Detection Using Unsupervised Learning: A Case Study of FPGA
Field programmable gate arrays (FPGAs) are widely used in critical applications such as industrial, medical, automotive, and military systems due to their ability to be dynamically reconfigured at runtime. However, this reconfigurability also presents security concerns, as FPGA designs are encoded in a bitstream that adversaries can target for design cloning, IP theft, or hardware Trojan insertion. This work presents a proof-of-concept for detecting hardware Trojans (HT) in FPGA using an unsupervised machine-learning method that eliminates the need for reference models of HT. The proposed method is based on transforming the configuration bitstream into an encoded vector, bypassing the need for netlist reconstruction and allowing for HT detection based solely on the extracted FPGA layout information. Our method was evaluated against various HT attack scenarios and accurately detected all infected bitstreams.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Metal Inter-layer Via Keep-out-zone in M3D IC: A Critical Process-aware Design Consideration HD2FPGA: Automated Framework for Accelerating Hyperdimensional Computing on FPGAs A Novel Stochastic LSTM Model Inspired by Quantum Machine Learning DC-Model: A New Method for Assisting the Analog Circuit Optimization Polynomial Formal Verification of a Processor: A RISC-V Case Study
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1