用于高速数字通信的模拟器

E. Fardin, P. Munro, Jarred Scagliotta, John Morris
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摘要

由于并行处理器通常受到可用的处理器间数据传输能力的限制,系统设计者通常试图将互连系统推到其带宽的极限。实用和经济的系统受到许多物理和包装考虑的限制,例如需要使用市售连接器。我们在这里描述visisolve -一个模拟器,我们已经建立了预测互连系统的行为,可以很容易地从“现成的”组件组装。它采用有限元方法预测网格单元内的动态电场。这些元件各部分的不规则几何形状,要求我们调整模拟中使用的网格,以适应实际连接器的需求——小尺寸、低插入力和自动组装——已经决定了导体的形状和路径。我们采用本征误差——直接计算H /spl次/H时,直接计算得到的电场与从/spl nabla//spl次/H得到的电场之间的差异作为需要改进的指标。
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A simulator for high speed digital communications
Since parallel processors are generally constrained by the available interprocessor data transfer capability, system designers generally try to push interconnection systems to their limits in bandwidth. Practical and economic systems are constrained by many physical and packaging considerations such as a need to use commercially available connectors. We describe here VisiSolve-a simulator that we have built to predict the behaviour of interconnect systems that can readily be assembled from 'off-the-shelf' components. It uses a finite element approach and predicts the dynamic electric field in the cells of the mesh. The irregular geometries of the individual parts of such components require us to adapt the mesh used in simulations in regions where the needs of a practical connector-small size, low insertion force and automatic assembly-have dictated the shape and path of the conductors. We have adopted a method which uses the constitutive error-the discrepancy between electric fields calculated directly and from /spl nabla//spl times/H when H was calculated directly/spl times/as an indicator that refinement is needed.
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