基于0.18 μm CMOS的6位1.6 GS/s Flash ADC

2006 IEEE Asian Solid-State Circuits Conference Pub Date : 2006-11-01 DOI:10.1109/ASSCC.2006.357919

Chien-Kai Hung, Jian-Feng Shiu, I. Chen, Hsin-Shu Chen

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引用次数: 14

摘要

在标准的0.18 μm CMOS工艺中，采用反向参考假体方法实现了一个6位1.6 GS/s的CMOS闪存ADC。该方法改善了偏置平均网络边界处的线性误差。该原型电路的INL为+0.32/-0.28 LSB, DNL为+0.28/-0.28 LSB。在奈奎斯特输入频率为1.6 GS/s时，SNDR和SFDR分别达到32和44 dB。ADC在1.8 V电源下消耗350mw，占用0.46 mm2的有效芯片面积。

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A 6-bit 1.6 GS/s Flash ADC in 0.18-μm CMOS with Reversed-Reference Dummy

A 6-bit 1.6 GS/s CMOS flash ADC using reversed-reference dummy method is demonstrated in a standard 0.18-μm CMOS process. The proposed method improves linearity error at the boundary of offset averaging networks. The prototype circuit exhibits an INL of +0.32/-0.28 LSB and a DNL of +0.28/-0.28 LSB. The SNDR and SFDR achieve 32 and 44 dB at 1.6 GS/s for Nyquist input frequency. The ADC consumes 350 mW at 1.8 V supply and occupies an active chip area of 0.46 mm2.

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2006 IEEE Asian Solid-State Circuits Conference

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