Register-Pressure Aware Predicator for Length Multiplier of RVV

The use of parallel processing with vector processors is indispensable. The RISC-V vector extension (RVV) is a highly anticipated extension due to the demand for growing AI applications. The modularity and extensibility make RISC-V a popular instruction set in the industry. Compared to SIMD instruction, vector instructions use fewer instructions with a larger register size which can handle multiple registers within one instruction, resulting in higher performance. With the vector grouping mechanism called vector length multiplier (LMUL) provided by RVV, RVV can combine multiple vector registers into one group so that the processor can increase the throughput of processing data under the same issue rate. However, due to the register pressure, the vector length is not always positively relative to the performance. Therefore, in this paper, we develop an LMUL predicator with register-pressure-aware models to accurately assign the proper LMUL for different programs. The algorithm is based on a priority-based register allocation algorithm and considers the cost of the register pressures and program use patterns. This design helps assign the proper vector length multiplier in compile time for RVV. The experiment result shows that, with a total of 76 vectorization cases of TSVC, the proposed register pressure aware length multiplier achieves 73 correct predictions of the optimal value of Length Multiplier.