用于人工耳蜗系统的1.3 v、9.1μW宽动态范围对数放大器

Y. Sundarasaradula, A. Thanachayanont
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引用次数: 2

摘要

提出了一种基于0.18μm CMOS工艺的低噪声、低功耗、宽动态范围的人工耳蜗系统CMOS对数放大器的设计与实现。所提出的对数放大器是基于真正的分段线性函数,采用渐进压缩并行求和结构。在1.3 V的单电源电压下,整个电路的功耗仅为9.1 μW。仿真的输入动态范围为80db,覆盖10 μV ~ 100mv的输入幅度。该放大器的模拟带宽为50hz ~ 24khz。模拟的总输入参考噪声为4.81 μV,积分范围为100 Hz ~ 10 kHz。
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A 1.3-V, 9.1μW wide-dynamic range logarithmic amplifier for cochlear implant system
This paper presents the design and realization of a low-noise, low-power, wide-dynamic-range CMOS logarithmic amplifier for cochlear implant system in a standard 0.18μm CMOS technology. The proposed logarithmic amplifier is based on the true piecewise linear function by using progressive-compression parallel-summation architecture. The overall circuit consumes only 9.1 μW from a 1.3 V single power supply voltage. The simulated input dynamic range is 80 dB, which covers the input amplitudes ranging from 10 μV to 100 mV. The simulated bandwidth of the amplifier is from 50 Hz to 24 kHz. The simulated total input-referred noise is 4.81 μV, integrated from 100 Hz to 10 kHz.
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