{"title":"通过65nm CMOS技术的三井导致ESD和锁存失效","authors":"D. Alvarez, W. Hartung, R. Bhandari","doi":"10.23919/EOS/ESD.2018.8509771","DOIUrl":null,"url":null,"abstract":"ESD and latch-up failures in a 65nm CMOS technology are presented where the triggering of a parasitic thyristor occurs despite the triple-well isolation that prevents the formation of a classical 4-layer SCR structure. The influence on triggering of the anode-to-cathode spacing, guard-ring protection and well resistances are studied for this type of parasitic device.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"ESD and Latch-up failures through triple-well in a 65nm CMOS technology\",\"authors\":\"D. Alvarez, W. Hartung, R. Bhandari\",\"doi\":\"10.23919/EOS/ESD.2018.8509771\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"ESD and latch-up failures in a 65nm CMOS technology are presented where the triggering of a parasitic thyristor occurs despite the triple-well isolation that prevents the formation of a classical 4-layer SCR structure. The influence on triggering of the anode-to-cathode spacing, guard-ring protection and well resistances are studied for this type of parasitic device.\",\"PeriodicalId\":328499,\"journal\":{\"name\":\"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)\",\"volume\":\"20 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/EOS/ESD.2018.8509771\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/EOS/ESD.2018.8509771","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
ESD and Latch-up failures through triple-well in a 65nm CMOS technology
ESD and latch-up failures in a 65nm CMOS technology are presented where the triggering of a parasitic thyristor occurs despite the triple-well isolation that prevents the formation of a classical 4-layer SCR structure. The influence on triggering of the anode-to-cathode spacing, guard-ring protection and well resistances are studied for this type of parasitic device.
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