3DIC时代的互联

Shenggao Li, M. Lin, Wei-Chih Chen, Chien-Chun Tsai
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引用次数: 3

摘要

自1959年MOSFET和1963年CMOS发明以来,CMOS电路成为低功率电池供电应用(如数字手表和便携式仪器)的首选技术。光刻缩放使CMOS能够在高性能计算领域竞争。Dennard在1974年对CMOS缩放原理的总结,进一步根据摩尔定律为微电子工业提供了科学的缩放方向。然而,到2005年,由于平面MOSFET上的亚阈值泄漏阻碍了Vth, Vdd和频率的缩放,Dennard缩放原理在很大程度上被打破。双栅极(SOI)和三栅极(FinFET)的发明可以更好地控制通道,从而使载流子不会逃逸到衬底上。栅极全能(例如:纳米线和纳米片)MOSFET的沟道被栅极电极包围,具有更好的静电控制,从而减少泄漏并提高载流子迁移率。使用多纳米片,单位面积内的有效W (W_eff)也得到了改善,与FinFet器件相比,允许适度的密度缩放。业界对CMOS缩放的进一步改进即将到来。ForkFET在PMOS和NMOS之间使用阻隔层,使PMOS和NMOS彼此放置得更近,从而提高晶体管密度,减少PMOS和NMOS之间的互连RC。互补场效应管(CFET)将PMOS和NMOS相互堆叠,由于垂直堆叠的互连比水平布线短得多,大大减少了PMOS和NMOS之间的互连。未来的技术进步可能允许更多层的mosfet单片制造(单片3D集成),当热和可测试性挑战得到更好的解决[1]-[9]。
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Interconnect in the Era of 3DIC
Since the invention of MOSFET in 1959, and CMOS in 1963, CMOS circuits emerged as the preferred technology for low power battery powered applications such as digital watches and portable instruments. Lithography scaling enabled CMOS to compete in high-performance computing subsequently. Dennard's 1974 summary on CMOS scaling principle further offered the microelectronics industry a scientific scaling direction according to Moore's Law. By 2005, Dennard scaling principle, however, largely broke down due to the subthreshold leakage on planar MOSFET which prevented the Vth, Vdd, and frequency to scale. Double-gate (SOI), and tri-gate (FinFET) were invented to allow the channel to be better controlled so carriers won't escape to the substrate. A gate-all-around (e.g.: nano-wire and nano-sheet) MOSFET has the channel surrounded by gate electrode with even better electrostatic control, leading to leakage reduction and improved carrier mobility. With multi nano-sheets, the effective W (W_eff) in a unit area is also improved, allowing moderate density scaling compared to FinFet devices. More improvement for CMOS scaling is on the horizon by the industry. ForkFET, which uses a barrier layer between PMOS and NMOS, allows the PMOS and NMOS to be placed closer to each other, thus improving transistor density and reducing interconnect RC between PMOS and NMOS. Complementary FET (CFET), which has PMOS and NMOS stacked on top of each other, reduces the interconnect between PMOS and NMOS significantly as the interconnect on vertical stacking is much shorter than horizontal wiring. Future technology advancement may allow more layers of MOSFETs to be manufactured monolithically (Monolithic 3D integration), when thermal and testability challenges are better solved [1]–[9].
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