Towards an Analytical Model of Latency in Deflection Routing: A Stochastic Process Approach for Bufferless NoCs

Performance analysis and design space exploration of bufferless Networks-on-Chip is done mainly through cycle accurate simulation which is time-consuming, while an analytical model seems out of reach for now. In order to raise the level of abstraction as well as capture the inherently probabilistic behavior of deflection routing, this paper presents a methodology for employing Markov chain models in the analysis of the behavior of bufferless Networks-on-Chip. A formal way of describing a bufferless NoC topology as a set of discrete-time Markov chains is presented. It is demonstrated that by combining this description with the network average distance, it is possible to obtain the expectation of the number of hops between any pair of nodes in the network as a function of the flit deflection probability. Comparisons between the proposed model and cycle-accurate simulation show that the proposed methodology achieves good accuracy at the useful injection rate range, with negligible computational cost.