{"title":"一种新型的高共模比低压电流输出级","authors":"Mohammad Hekmat Kashtiban, S. J. Azhari","doi":"10.1109/ISSCS.2009.5206137","DOIUrl":null,"url":null,"abstract":"In this work a novel CMOS Current Output Stage (COS) is presented whose Common-Mode Rejection Ratio is remarkably increased exploiting a novel Common Mode Feed Forward (CMFF) technique to compensate the output common mode signal. The complete stage is designed in 0.13µm technology and simulated with ADS and Hspice. The proposed COS achieved 105dB CMRR and 85dB PSRR while can work under ±1V power supply. Compared to the traditional COS the CMRR and PSRR improvement are higher than 50dB and 30dB respectively.","PeriodicalId":277587,"journal":{"name":"2009 International Symposium on Signals, Circuits and Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"A novel high CMRR low voltage current output stage\",\"authors\":\"Mohammad Hekmat Kashtiban, S. J. Azhari\",\"doi\":\"10.1109/ISSCS.2009.5206137\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work a novel CMOS Current Output Stage (COS) is presented whose Common-Mode Rejection Ratio is remarkably increased exploiting a novel Common Mode Feed Forward (CMFF) technique to compensate the output common mode signal. The complete stage is designed in 0.13µm technology and simulated with ADS and Hspice. The proposed COS achieved 105dB CMRR and 85dB PSRR while can work under ±1V power supply. Compared to the traditional COS the CMRR and PSRR improvement are higher than 50dB and 30dB respectively.\",\"PeriodicalId\":277587,\"journal\":{\"name\":\"2009 International Symposium on Signals, Circuits and Systems\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-07-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 International Symposium on Signals, Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCS.2009.5206137\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Symposium on Signals, Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCS.2009.5206137","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A novel high CMRR low voltage current output stage
In this work a novel CMOS Current Output Stage (COS) is presented whose Common-Mode Rejection Ratio is remarkably increased exploiting a novel Common Mode Feed Forward (CMFF) technique to compensate the output common mode signal. The complete stage is designed in 0.13µm technology and simulated with ADS and Hspice. The proposed COS achieved 105dB CMRR and 85dB PSRR while can work under ±1V power supply. Compared to the traditional COS the CMRR and PSRR improvement are higher than 50dB and 30dB respectively.
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