High speed FIR Filter design based on sharing multiplication using dual channel adder and compressor

This paper presents a novel architecture for a high speed finite impulse response (FIR) filter. The design of proposed filter is based on a computation sharing multiplier algorithm with reduced addition implementation. The proposed filter is very efficient, as it gives a significant improvement in speed with a reduction in size of adder circuits. The performance of the proposed filter is compared with implementation based on carry save multiplier in 0.13 mum technology. The proposed filter improves speed by approximately 50% with respect to FIR filter implementations based on carry-save multiplier.