{"title":"基于事务级建模的SoC设计流程中PSL属性复用研究","authors":"N. Bombieri, A. Fedeli, F. Fummi","doi":"10.1109/MTV.2005.15","DOIUrl":null,"url":null,"abstract":"In this paper the authors present some key concepts concerning the properties specification language (PSL) utilization in a system level verification flow for system on chip (SoC) designs. As transaction level modeling (TLM) is the de-facto reference model for SoC design flow, the authors evaluate PSL adoption in TLM context. How to save time and effort in the verification phase during system development steps and how to overcome global system verification limitations through a compositional approach are discussed. Two PSL-based techniques, \"properties re-use\" and \"properties refinement\", are described and compared in terms of refinement effort and simulation speed delay","PeriodicalId":179953,"journal":{"name":"2005 Sixth International Workshop on Microprocessor Test and Verification","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2005-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"20","resultStr":"{\"title\":\"On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling\",\"authors\":\"N. Bombieri, A. Fedeli, F. Fummi\",\"doi\":\"10.1109/MTV.2005.15\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper the authors present some key concepts concerning the properties specification language (PSL) utilization in a system level verification flow for system on chip (SoC) designs. As transaction level modeling (TLM) is the de-facto reference model for SoC design flow, the authors evaluate PSL adoption in TLM context. How to save time and effort in the verification phase during system development steps and how to overcome global system verification limitations through a compositional approach are discussed. Two PSL-based techniques, \\\"properties re-use\\\" and \\\"properties refinement\\\", are described and compared in terms of refinement effort and simulation speed delay\",\"PeriodicalId\":179953,\"journal\":{\"name\":\"2005 Sixth International Workshop on Microprocessor Test and Verification\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-11-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"20\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2005 Sixth International Workshop on Microprocessor Test and Verification\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MTV.2005.15\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 Sixth International Workshop on Microprocessor Test and Verification","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MTV.2005.15","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling
In this paper the authors present some key concepts concerning the properties specification language (PSL) utilization in a system level verification flow for system on chip (SoC) designs. As transaction level modeling (TLM) is the de-facto reference model for SoC design flow, the authors evaluate PSL adoption in TLM context. How to save time and effort in the verification phase during system development steps and how to overcome global system verification limitations through a compositional approach are discussed. Two PSL-based techniques, "properties re-use" and "properties refinement", are described and compared in terms of refinement effort and simulation speed delay