Radu-Valentin Petrica, Mihaela-Daniela Dobre, P. Coll, F. Draghici, G. Brezeanu
{"title":"电平移位器体系结构的比较:在I/O单元中的应用","authors":"Radu-Valentin Petrica, Mihaela-Daniela Dobre, P. Coll, F. Draghici, G. Brezeanu","doi":"10.1109/SMICND.2018.8539796","DOIUrl":null,"url":null,"abstract":"Novel low-voltage and high-speed level shifter topologies will be presented. The level shifters circuits were designed in 40 nm technology using 1.2V devices and zero-VT transistors. These techniques will provide functionality near the threshold region. The simulated results were compared with a reference architecture. The resulted level shifters will be integrated in an already tested I/O structure. The results were analyzed in terms of electrical performance and silicon area.","PeriodicalId":247062,"journal":{"name":"2018 International Semiconductor Conference (CAS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Comparison of Level Shifter Architectures: Application to I/O Cell\",\"authors\":\"Radu-Valentin Petrica, Mihaela-Daniela Dobre, P. Coll, F. Draghici, G. Brezeanu\",\"doi\":\"10.1109/SMICND.2018.8539796\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Novel low-voltage and high-speed level shifter topologies will be presented. The level shifters circuits were designed in 40 nm technology using 1.2V devices and zero-VT transistors. These techniques will provide functionality near the threshold region. The simulated results were compared with a reference architecture. The resulted level shifters will be integrated in an already tested I/O structure. The results were analyzed in terms of electrical performance and silicon area.\",\"PeriodicalId\":247062,\"journal\":{\"name\":\"2018 International Semiconductor Conference (CAS)\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 International Semiconductor Conference (CAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SMICND.2018.8539796\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 International Semiconductor Conference (CAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMICND.2018.8539796","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Comparison of Level Shifter Architectures: Application to I/O Cell
Novel low-voltage and high-speed level shifter topologies will be presented. The level shifters circuits were designed in 40 nm technology using 1.2V devices and zero-VT transistors. These techniques will provide functionality near the threshold region. The simulated results were compared with a reference architecture. The resulted level shifters will be integrated in an already tested I/O structure. The results were analyzed in terms of electrical performance and silicon area.
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