Narcizo Sabbatini, Antonio Mauricio Brochi, Tulio Ibanez Nunes
{"title":"嵌入式MCU内核验证中的复用问题","authors":"Narcizo Sabbatini, Antonio Mauricio Brochi, Tulio Ibanez Nunes","doi":"10.1109/ICCDCS.2002.1004000","DOIUrl":null,"url":null,"abstract":"The main issues related to the verification of cores embedded in a microcontroller unit (MCU) are addressed in this paper. Issues such as verification environment design, simulation pattern strategies and reuse, as well as standalone and chip level verification are discussed. An analysis of the verification environment is performed from the perspective of the reuse across the design cycle, focussing on the core standalone and on the chip level verification. A case study analysis is included.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"414 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Reuse issues on the verification of embedded MCU cores\",\"authors\":\"Narcizo Sabbatini, Antonio Mauricio Brochi, Tulio Ibanez Nunes\",\"doi\":\"10.1109/ICCDCS.2002.1004000\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The main issues related to the verification of cores embedded in a microcontroller unit (MCU) are addressed in this paper. Issues such as verification environment design, simulation pattern strategies and reuse, as well as standalone and chip level verification are discussed. An analysis of the verification environment is performed from the perspective of the reuse across the design cycle, focussing on the core standalone and on the chip level verification. A case study analysis is included.\",\"PeriodicalId\":416680,\"journal\":{\"name\":\"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)\",\"volume\":\"414 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCDCS.2002.1004000\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCDCS.2002.1004000","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Reuse issues on the verification of embedded MCU cores
The main issues related to the verification of cores embedded in a microcontroller unit (MCU) are addressed in this paper. Issues such as verification environment design, simulation pattern strategies and reuse, as well as standalone and chip level verification are discussed. An analysis of the verification environment is performed from the perspective of the reuse across the design cycle, focussing on the core standalone and on the chip level verification. A case study analysis is included.