A 500 MHz 32-word X 64-bit 8-port Self-resetting CMOS Register File And Associated Dynamic-to-static Latch

The advent of superscalar architectures for microprocessors has created the need for register files having many ports. Such multi-porting is at odds with the universal goals of high-density, high-performanc,e, and %e of testing. High-density multi-porting favors single-ended reading and wnting. However, single-ended operation makes high-performance more difficult to achieve. Another issue in VLSI is how to test the numerous embedded arrays. Typically, large memory arrays employ ABIST circuiuy. However, for small arrays, such as register files, the overhead of ABIST is more significant for performance and area, and thus is less acceptable. With this background we have set out to design a 2-write/6-read-port 32 x 64-bit register file which is dense AND fast AND readily testable in a 2.5-V 0.5-pm CMOS technology. Our approach employs self-resetting CMOS (SRCMOS) dynamic circuits [I]. Special attention has been paid toward insuring design robustness with regard to input pulsewidth variations. The testing issue has been dealt with up-front by making the memory cells totally LSSD compatible. Also designed was a dynamic-to-static latch which can be employed to make the register file compatible with either a dynamic or static dataflow.