{"title":"面向多核平台的可靠实时任务执行方案","authors":"T. Yoneda, Masashi Imai, H. Saito, Kenji Kise","doi":"10.1109/DFT.2015.7315162","DOIUrl":null,"url":null,"abstract":"This paper explores a new dependable real-time task execution scheme for a many-core system. This scheme is based on duplication with temporary TMR and reconfiguration. Unlike a common scheme with several spare units, every processor core in our scheme is used for task execution. Thus, redundant processor cores contribute to both the reliability and performance of the entire system. We first show the implementation details of our scheme. Then the proposed scheme is analytically evaluated using abstracted models and compared with two other schemes.","PeriodicalId":383972,"journal":{"name":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Dependable real-time task execution scheme for a many-core platform\",\"authors\":\"T. Yoneda, Masashi Imai, H. Saito, Kenji Kise\",\"doi\":\"10.1109/DFT.2015.7315162\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper explores a new dependable real-time task execution scheme for a many-core system. This scheme is based on duplication with temporary TMR and reconfiguration. Unlike a common scheme with several spare units, every processor core in our scheme is used for task execution. Thus, redundant processor cores contribute to both the reliability and performance of the entire system. We first show the implementation details of our scheme. Then the proposed scheme is analytically evaluated using abstracted models and compared with two other schemes.\",\"PeriodicalId\":383972,\"journal\":{\"name\":\"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)\",\"volume\":\"81 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DFT.2015.7315162\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFT.2015.7315162","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Dependable real-time task execution scheme for a many-core platform
This paper explores a new dependable real-time task execution scheme for a many-core system. This scheme is based on duplication with temporary TMR and reconfiguration. Unlike a common scheme with several spare units, every processor core in our scheme is used for task execution. Thus, redundant processor cores contribute to both the reliability and performance of the entire system. We first show the implementation details of our scheme. Then the proposed scheme is analytically evaluated using abstracted models and compared with two other schemes.
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