130纳米CMOS的二次谐波60 ghz功率放大器

J. Wernehag, H. Sjöland
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摘要

比较了两种不同的倍频功率放大器拓扑结构,一种是差分输入,一种是单端输入,两种都是60 GHz的单端输出。倍频能力至少从两个角度来看是有价值的,1)高频信号尽可能少地出现在芯片上,2)压控振荡器和功率放大器处于不同的频率,缓解了收发器中两者的隔离。该拓扑结构已在1p8M 130纳米CMOS工艺中进行了模拟。谐振节点用片上传输线调谐。这些都在ADS中进行了模拟,并与标准的Cadence组件tline3进行了比较。节奏分量对传输线的损耗给出了比较悲观的估计。单端输入放大器输出最大3.7 dBm,从1.2 V电源吸取27 mA,而差分输入放大器输出5.0 dBm,吸取28 mA。比较了两种不同的倍频功率放大器拓扑结构,一种是差分输入,一种是单端输入,两种都是60 GHz的单端输出。倍频能力至少从两个角度来看是有价值的,1)高频信号尽可能少地出现在芯片上,2)压控振荡器和功率放大器处于不同的频率,缓解了收发器中两者的隔离。该拓扑结构已在1p8M 130纳米CMOS工艺中进行了模拟。谐振节点用片上传输线调谐。这些都在ADS中进行了模拟,并与标准的Cadence组件tline3进行了比较。节奏分量对传输线的损耗给出了比较悲观的估计。单端输入放大器输出最大3.7 dBm,从1.2 V电源吸取27 mA,而差分输入放大器输出5.0 dBm,吸取28 mA。放大器的3db带宽分别为5.9 GHz和6.8 GHz。放大器的3db带宽分别为5.9 GHz和6.8 GHz。
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Second harmonic 60-GHz power amplifiers in 130-nm CMOS
Two different frequency doubling power amplifier topologies have been compared, one with differential input and one with single-ended, both with single-ended output at 60 GHz. The frequency doubling capability is valuable from at least two perspectives, 1) the high frequency signal is on the chip as little as possible 2) the voltage controlled oscillator and power amplifier are at different frequencies easing the isolation of the two in a transceiver. The topologies have been simulated in a 1p8M 130-nm CMOS process. The resonant nodes are tuned with on-chip transmission lines. These have been simulated in ADS and compared to a standard Cadence component, tline3. The Cadence component gives a somewhat pessimistic estimation of the losses in the transmission line. The single ended input amplifier outputs a maximum of 3.7 dBm and draws 27 mA from a 1.2 V supply, while the one with differential input outputs 5.0 dBm and draws 28 mA. TTwo different frequency doubling power amplifier topologies have been compared, one with differential input and one with single-ended, both with single-ended output at 60 GHz. The frequency doubling capability is valuable from at least two perspectives, 1) the high frequency signal is on the chip as little as possible 2) the voltage controlled oscillator and power amplifier are at different frequencies easing the isolation of the two in a transceiver. The topologies have been simulated in a 1p8M 130-nm CMOS process. The resonant nodes are tuned with on-chip transmission lines. These have been simulated in ADS and compared to a standard Cadence component, tline3. The Cadence component gives a somewhat pessimistic estimation of the losses in the transmission line. The single ended input amplifier outputs a maximum of 3.7 dBm and draws 27 mA from a 1.2 V supply, while the one with differential input outputs 5.0 dBm and draws 28 mA. The 3-dB bandwidth of the amplifiers are 5.9 GHz and 6.8 GHz, respectively.he 3-dB bandwidth of the amplifiers are 5.9 GHz and 6.8 GHz, respectively.
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