{"title":"一种4mbit沟槽DRAM技术功能测试制造/表征策略","authors":"C. Long, S. Voldman","doi":"10.1109/ISMSS.1990.66113","DOIUrl":null,"url":null,"abstract":"The authors discuss a 4-Mb substrate-plate-trench (SPT) DRAM (dynamic random access memory) technology applying an innovative manufacturing test strategy using the technology product chip, an addressable diagnostic monitor (ADM), and trench DC macroarray test structures. This manufacturing functional test strategy is effective in achieving process optimization, defect characterization, and high retention yield in a DRAM trench technology. Examples of the strategy's application in various situations and at different development stages are shown.<<ETX>>","PeriodicalId":398535,"journal":{"name":"IEEE/SEMI International Symposium on Semiconductor Manufacturing Science","volume":"53 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A 4-Mbit trench DRAM technology functional test manufacturing/characterization strategy\",\"authors\":\"C. Long, S. Voldman\",\"doi\":\"10.1109/ISMSS.1990.66113\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors discuss a 4-Mb substrate-plate-trench (SPT) DRAM (dynamic random access memory) technology applying an innovative manufacturing test strategy using the technology product chip, an addressable diagnostic monitor (ADM), and trench DC macroarray test structures. This manufacturing functional test strategy is effective in achieving process optimization, defect characterization, and high retention yield in a DRAM trench technology. Examples of the strategy's application in various situations and at different development stages are shown.<<ETX>>\",\"PeriodicalId\":398535,\"journal\":{\"name\":\"IEEE/SEMI International Symposium on Semiconductor Manufacturing Science\",\"volume\":\"53 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-05-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE/SEMI International Symposium on Semiconductor Manufacturing Science\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISMSS.1990.66113\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE/SEMI International Symposium on Semiconductor Manufacturing Science","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMSS.1990.66113","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 4-Mbit trench DRAM technology functional test manufacturing/characterization strategy
The authors discuss a 4-Mb substrate-plate-trench (SPT) DRAM (dynamic random access memory) technology applying an innovative manufacturing test strategy using the technology product chip, an addressable diagnostic monitor (ADM), and trench DC macroarray test structures. This manufacturing functional test strategy is effective in achieving process optimization, defect characterization, and high retention yield in a DRAM trench technology. Examples of the strategy's application in various situations and at different development stages are shown.<>
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