Pub Date : 1990-05-21DOI: 10.1109/ISMSS.1990.66130
P. Gavaskar, E. Maass, L. Weldy, H. Nguyen
Applying voice recognition technology to a manufacturing environment has provided an advanced and practical means of data collection. Accurate real-time data are gathered without the use of labor-intensive paperwork and data entry. In the manufacturing of integrated circuits at Motorola, voice technology has proved to be beneficial in the inspection process, where hands and eyes remain busy performing the primary task. The integration of voice-recognition technology with the inspection process, as implemented in the Voice Activated Data Entry System (VADES), allowed the information to be recorded and entered into a database without interruption of the inspection process. This resulted in a 23% improvement in productivity, elimination of nonvalue-added clerical tasks, and immediate availability of inspection information. Data accuracy achieved was 100%. The system received excellent acceptance from the inspectors.<>
{"title":"Integrating voice recognition technology with inspection of integrated circuits","authors":"P. Gavaskar, E. Maass, L. Weldy, H. Nguyen","doi":"10.1109/ISMSS.1990.66130","DOIUrl":"https://doi.org/10.1109/ISMSS.1990.66130","url":null,"abstract":"Applying voice recognition technology to a manufacturing environment has provided an advanced and practical means of data collection. Accurate real-time data are gathered without the use of labor-intensive paperwork and data entry. In the manufacturing of integrated circuits at Motorola, voice technology has proved to be beneficial in the inspection process, where hands and eyes remain busy performing the primary task. The integration of voice-recognition technology with the inspection process, as implemented in the Voice Activated Data Entry System (VADES), allowed the information to be recorded and entered into a database without interruption of the inspection process. This resulted in a 23% improvement in productivity, elimination of nonvalue-added clerical tasks, and immediate availability of inspection information. Data accuracy achieved was 100%. The system received excellent acceptance from the inspectors.<<ETX>>","PeriodicalId":398535,"journal":{"name":"IEEE/SEMI International Symposium on Semiconductor Manufacturing Science","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127504375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-21DOI: 10.1109/ISMSS.1990.66109
P. Thomas
The creation of the competitive mindset in a company using total cycle time reduction techniques is described. Total cycle time is the combined effect of the cycle times of all business processes, from the time a need exists until it is satisfied. It drives three key elements of competitiveness: responsiveness, results acceleration, and resource minimization. It is concluded that total cycle time reduction forces quality improvements to the bottom line. This reduction provides a real-time, continuous, positive, internal sense of urgency, without the need for a crisis, thereby removing the high-leverage business process and culture barriers to competitiveness.<>
{"title":"The competitive mindset-using total cycle time to cut through the clutter and confusion","authors":"P. Thomas","doi":"10.1109/ISMSS.1990.66109","DOIUrl":"https://doi.org/10.1109/ISMSS.1990.66109","url":null,"abstract":"The creation of the competitive mindset in a company using total cycle time reduction techniques is described. Total cycle time is the combined effect of the cycle times of all business processes, from the time a need exists until it is satisfied. It drives three key elements of competitiveness: responsiveness, results acceleration, and resource minimization. It is concluded that total cycle time reduction forces quality improvements to the bottom line. This reduction provides a real-time, continuous, positive, internal sense of urgency, without the need for a crisis, thereby removing the high-leverage business process and culture barriers to competitiveness.<<ETX>>","PeriodicalId":398535,"journal":{"name":"IEEE/SEMI International Symposium on Semiconductor Manufacturing Science","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128243060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-21DOI: 10.1109/ISMSS.1990.66122
M. Flaherty
An intensive study of over 20 high-volume VLSI fabrication facilities located in Japan and the United States is described. The purpose of the study is to learn what managers can do to make the facilities perform better in terms of productivity, process advance, and the introduction and production of products with advanced performance. The author describes the methodology of the study as well as a conceptual model of manufacturing and engineering management which structures some of the empirical work.<>
{"title":"Managing manufacturing and engineering in VLSI fabs","authors":"M. Flaherty","doi":"10.1109/ISMSS.1990.66122","DOIUrl":"https://doi.org/10.1109/ISMSS.1990.66122","url":null,"abstract":"An intensive study of over 20 high-volume VLSI fabrication facilities located in Japan and the United States is described. The purpose of the study is to learn what managers can do to make the facilities perform better in terms of productivity, process advance, and the introduction and production of products with advanced performance. The author describes the methodology of the study as well as a conceptual model of manufacturing and engineering management which structures some of the empirical work.<<ETX>>","PeriodicalId":398535,"journal":{"name":"IEEE/SEMI International Symposium on Semiconductor Manufacturing Science","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125746096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-21DOI: 10.1109/ISMSS.1990.66113
C. Long, S. Voldman
The authors discuss a 4-Mb substrate-plate-trench (SPT) DRAM (dynamic random access memory) technology applying an innovative manufacturing test strategy using the technology product chip, an addressable diagnostic monitor (ADM), and trench DC macroarray test structures. This manufacturing functional test strategy is effective in achieving process optimization, defect characterization, and high retention yield in a DRAM trench technology. Examples of the strategy's application in various situations and at different development stages are shown.<>
{"title":"A 4-Mbit trench DRAM technology functional test manufacturing/characterization strategy","authors":"C. Long, S. Voldman","doi":"10.1109/ISMSS.1990.66113","DOIUrl":"https://doi.org/10.1109/ISMSS.1990.66113","url":null,"abstract":"The authors discuss a 4-Mb substrate-plate-trench (SPT) DRAM (dynamic random access memory) technology applying an innovative manufacturing test strategy using the technology product chip, an addressable diagnostic monitor (ADM), and trench DC macroarray test structures. This manufacturing functional test strategy is effective in achieving process optimization, defect characterization, and high retention yield in a DRAM trench technology. Examples of the strategy's application in various situations and at different development stages are shown.<<ETX>>","PeriodicalId":398535,"journal":{"name":"IEEE/SEMI International Symposium on Semiconductor Manufacturing Science","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131013068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-21DOI: 10.1109/ISMSS.1990.66123
P. Castrucci
Four integration trends in semiconductor manufacturing are discussed: simulation-controlled fabricators, integrated process tools, integrated yield management systems, and integrated SMART/microenvironment production lines. Specific examples are used to explain the value of these four technologies in the fab of the 1990s, characterizing these paradigms by short cycle times, high yields, low inventories, high throughput, continuous-flow production, dynamic capacity reconfiguration, high-quality/zero-defect products, tight statistical control, and low cost. It is projected that the causes for accelerating adaptation to this new type of fab will shift the semiconductor paradigms from manual factories to integrated production lines.<>
{"title":"Emerging paradigms in semiconductor manufacturing","authors":"P. Castrucci","doi":"10.1109/ISMSS.1990.66123","DOIUrl":"https://doi.org/10.1109/ISMSS.1990.66123","url":null,"abstract":"Four integration trends in semiconductor manufacturing are discussed: simulation-controlled fabricators, integrated process tools, integrated yield management systems, and integrated SMART/microenvironment production lines. Specific examples are used to explain the value of these four technologies in the fab of the 1990s, characterizing these paradigms by short cycle times, high yields, low inventories, high throughput, continuous-flow production, dynamic capacity reconfiguration, high-quality/zero-defect products, tight statistical control, and low cost. It is projected that the causes for accelerating adaptation to this new type of fab will shift the semiconductor paradigms from manual factories to integrated production lines.<<ETX>>","PeriodicalId":398535,"journal":{"name":"IEEE/SEMI International Symposium on Semiconductor Manufacturing Science","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133439051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-21DOI: 10.1109/ISMSS.1990.66112
A. Gerbens
The concepts of Poka Yoke (mistake-proofing) and source inspection have been applied to two digital bipolar integrated-circuit processing steps: sputter etch (prior to metal deposition) and wet etch of oxide. In both applications, the opportunities for error were identified, and error-prevention techniques were defined to eliminate the potential for error at the source. The sputter etch application involves embedding a microprocessor into an MRC-903 sputtering system. The operator interacts with the microprocessor, which provides set-up assistance and monitors the quality of the sputter etch process. Deposition of metal is not allowed if the sputter etch does not meet minimum processing specifications. The probability of defects (high-resistance via contacts) is greatly reduced: these defects could otherwise remain undetected until later electrical testing. The wet oxide etch application uses a stand-alone microcomputer to provide expert assistance to the production operator. The assistance provides help with etchant qualification, special instructions associated with difficult process requirements, location of areas to be measured, specified process control limits, and calculation of etch times. This microcomputer implementation allows the retention of a relatively complicated process sequence while minimizing the occurrence of wafer loss due to human error.<>
{"title":"Introduction of Poka Yoke techniques in a bipolar fab","authors":"A. Gerbens","doi":"10.1109/ISMSS.1990.66112","DOIUrl":"https://doi.org/10.1109/ISMSS.1990.66112","url":null,"abstract":"The concepts of Poka Yoke (mistake-proofing) and source inspection have been applied to two digital bipolar integrated-circuit processing steps: sputter etch (prior to metal deposition) and wet etch of oxide. In both applications, the opportunities for error were identified, and error-prevention techniques were defined to eliminate the potential for error at the source. The sputter etch application involves embedding a microprocessor into an MRC-903 sputtering system. The operator interacts with the microprocessor, which provides set-up assistance and monitors the quality of the sputter etch process. Deposition of metal is not allowed if the sputter etch does not meet minimum processing specifications. The probability of defects (high-resistance via contacts) is greatly reduced: these defects could otherwise remain undetected until later electrical testing. The wet oxide etch application uses a stand-alone microcomputer to provide expert assistance to the production operator. The assistance provides help with etchant qualification, special instructions associated with difficult process requirements, location of areas to be measured, specified process control limits, and calculation of etch times. This microcomputer implementation allows the retention of a relatively complicated process sequence while minimizing the occurrence of wafer loss due to human error.<<ETX>>","PeriodicalId":398535,"journal":{"name":"IEEE/SEMI International Symposium on Semiconductor Manufacturing Science","volume":"194 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122364649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-21DOI: 10.1109/ISMSS.1990.66131
B. Tullis, Vijay Mehrotra, D. Zuanich
A chief limitation on process development cycle time is the time it takes to process wafers. Hewlett Packard Co. has shortened this time by using discrete-event simulation of its R&D fabrication facility to better understand its capacity limitations and to analyze how changes affect the cycle times of complete wafer processing. Results include Pareto charts of equipment according to the impacts that changes in their mean-time-between-failure (MTBF) and/or mean-time-to-repair (MTTR) parameters have on wafer cycle times. Results also include a Pareto chart of operator skills and their impact on cycle times; that is, one can know how much effect there is on cycle times when staffing is changed to satisfy needs for a specific operator skill. Similarly, it is possible to evaluate effects of shift schedules and end-of-shift wafer processing decisions. Furthermore, simulation reveals the relative benefits of applying different dispatching rules (such as first in, first out, shortest-processing time, least-work-in-next queue, etc.) and of different inventory-level control policies.<>
{"title":"Successful modeling of a semiconductor R&D facility","authors":"B. Tullis, Vijay Mehrotra, D. Zuanich","doi":"10.1109/ISMSS.1990.66131","DOIUrl":"https://doi.org/10.1109/ISMSS.1990.66131","url":null,"abstract":"A chief limitation on process development cycle time is the time it takes to process wafers. Hewlett Packard Co. has shortened this time by using discrete-event simulation of its R&D fabrication facility to better understand its capacity limitations and to analyze how changes affect the cycle times of complete wafer processing. Results include Pareto charts of equipment according to the impacts that changes in their mean-time-between-failure (MTBF) and/or mean-time-to-repair (MTTR) parameters have on wafer cycle times. Results also include a Pareto chart of operator skills and their impact on cycle times; that is, one can know how much effect there is on cycle times when staffing is changed to satisfy needs for a specific operator skill. Similarly, it is possible to evaluate effects of shift schedules and end-of-shift wafer processing decisions. Furthermore, simulation reveals the relative benefits of applying different dispatching rules (such as first in, first out, shortest-processing time, least-work-in-next queue, etc.) and of different inventory-level control policies.<<ETX>>","PeriodicalId":398535,"journal":{"name":"IEEE/SEMI International Symposium on Semiconductor Manufacturing Science","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134336796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-21DOI: 10.1109/ISMSS.1990.66124
Y. Mizokami
A CIM (computer-integrated manufacturing) system implemented in a plant for memory-device production is described. It is noted that application of this system is making it possible to prevent operational error, to reduce manpower, and to improve quality control. After the installation of an ultraclean process, a high-yield VLSI plant with fewer operators was realized.<>
{"title":"The total CIM system for semiconductor plants","authors":"Y. Mizokami","doi":"10.1109/ISMSS.1990.66124","DOIUrl":"https://doi.org/10.1109/ISMSS.1990.66124","url":null,"abstract":"A CIM (computer-integrated manufacturing) system implemented in a plant for memory-device production is described. It is noted that application of this system is making it possible to prevent operational error, to reduce manpower, and to improve quality control. After the installation of an ultraclean process, a high-yield VLSI plant with fewer operators was realized.<<ETX>>","PeriodicalId":398535,"journal":{"name":"IEEE/SEMI International Symposium on Semiconductor Manufacturing Science","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121682602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-21DOI: 10.1109/ISMSS.1990.66126
B. L. Farrell
The author describes a production performance database that allows engineers and shop managers of integrated-circuit factories to monitor the performance of their facilities. The database combines actual processing data from the production systems with estimates of processing times to give a measure of how efficiently the facilities are being used. In addition, the database contains other performance measures such as queuing delays and production time variances. The users access the data through two menu-driven programs. One program uses window-based software to display the clean room areas, facilities, and facility groups for which data are available. The user needs only to type a single-word command to run the software and is prompted for all inputs through menus. The other program is an interactive report generator that allows the user to customize a report to suit his or her needs. The program leads the user through a series of questions to determine which area, time interval, performance measures, and report formats he or she would like to use. Engineers and shop managers have used both programs to track the performance of particular facilities and facility groups and to identify problem areas.<>
{"title":"A production performance database and query software for integrated circuit manufacturing","authors":"B. L. Farrell","doi":"10.1109/ISMSS.1990.66126","DOIUrl":"https://doi.org/10.1109/ISMSS.1990.66126","url":null,"abstract":"The author describes a production performance database that allows engineers and shop managers of integrated-circuit factories to monitor the performance of their facilities. The database combines actual processing data from the production systems with estimates of processing times to give a measure of how efficiently the facilities are being used. In addition, the database contains other performance measures such as queuing delays and production time variances. The users access the data through two menu-driven programs. One program uses window-based software to display the clean room areas, facilities, and facility groups for which data are available. The user needs only to type a single-word command to run the software and is prompted for all inputs through menus. The other program is an interactive report generator that allows the user to customize a report to suit his or her needs. The program leads the user through a series of questions to determine which area, time interval, performance measures, and report formats he or she would like to use. Engineers and shop managers have used both programs to track the performance of particular facilities and facility groups and to identify problem areas.<<ETX>>","PeriodicalId":398535,"journal":{"name":"IEEE/SEMI International Symposium on Semiconductor Manufacturing Science","volume":"07 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130176157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-21DOI: 10.1109/ISMSS.1990.66121
J. Zuk
Operation costing is shown to be a useful method for accurately allocating product costs in a fair manner. Manufacturing complexities such as shared facilities, dynamic product routings, and complex batching/dispatching rules, which often plague traditional costing techniques and result in erroneous information, may be handled in a straightforward manner. The technique allocates all costs based on actual resource utilization, thus accurately capturing the impact of product mix on final product cost. The technique is robust in its application: that is, it may be adopted for both a cost measurement system and a cost planning/evaluation system.<>
{"title":"Techniques for effective product costing in an IC manufacturing facility","authors":"J. Zuk","doi":"10.1109/ISMSS.1990.66121","DOIUrl":"https://doi.org/10.1109/ISMSS.1990.66121","url":null,"abstract":"Operation costing is shown to be a useful method for accurately allocating product costs in a fair manner. Manufacturing complexities such as shared facilities, dynamic product routings, and complex batching/dispatching rules, which often plague traditional costing techniques and result in erroneous information, may be handled in a straightforward manner. The technique allocates all costs based on actual resource utilization, thus accurately capturing the impact of product mix on final product cost. The technique is robust in its application: that is, it may be adopted for both a cost measurement system and a cost planning/evaluation system.<<ETX>>","PeriodicalId":398535,"journal":{"name":"IEEE/SEMI International Symposium on Semiconductor Manufacturing Science","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132598208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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