{"title":"一种新的MOS器件片上辐照后退火集成测试结构","authors":"C. Chabrerie, J. Autran, O. Flament, J. Boudenot","doi":"10.1109/RADECS.1997.698896","DOIUrl":null,"url":null,"abstract":"We have developed a prototype test structure (named THERMOS) demonstrating the feasibility and the interest of the on-chip heating in a Silicon-On-Insulator technology. This circuit has been specially designed for the study of post-irradiation effects in a radiation-hardened CMOS technology. Preliminary results are presented here for the on-chip annealing of irradiated n-channel transistors.","PeriodicalId":106774,"journal":{"name":"RADECS 97. Fourth European Conference on Radiation and its Effects on Components and Systems (Cat. No.97TH8294)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A new integrated test structure for on-chip post-irradiation annealing in MOS devices\",\"authors\":\"C. Chabrerie, J. Autran, O. Flament, J. Boudenot\",\"doi\":\"10.1109/RADECS.1997.698896\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We have developed a prototype test structure (named THERMOS) demonstrating the feasibility and the interest of the on-chip heating in a Silicon-On-Insulator technology. This circuit has been specially designed for the study of post-irradiation effects in a radiation-hardened CMOS technology. Preliminary results are presented here for the on-chip annealing of irradiated n-channel transistors.\",\"PeriodicalId\":106774,\"journal\":{\"name\":\"RADECS 97. Fourth European Conference on Radiation and its Effects on Components and Systems (Cat. No.97TH8294)\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-09-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"RADECS 97. Fourth European Conference on Radiation and its Effects on Components and Systems (Cat. No.97TH8294)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RADECS.1997.698896\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"RADECS 97. Fourth European Conference on Radiation and its Effects on Components and Systems (Cat. No.97TH8294)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RADECS.1997.698896","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A new integrated test structure for on-chip post-irradiation annealing in MOS devices
We have developed a prototype test structure (named THERMOS) demonstrating the feasibility and the interest of the on-chip heating in a Silicon-On-Insulator technology. This circuit has been specially designed for the study of post-irradiation effects in a radiation-hardened CMOS technology. Preliminary results are presented here for the on-chip annealing of irradiated n-channel transistors.
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