A. Boudabous, A. Ben Atitallah, P. Kadionik, L. Khriji, N. Masmoudi
{"title":"HW/SW FPGA实现矢量中值滤波器","authors":"A. Boudabous, A. Ben Atitallah, P. Kadionik, L. Khriji, N. Masmoudi","doi":"10.1109/RME.2007.4401821","DOIUrl":null,"url":null,"abstract":"In this paper, we present an efficient hardware/software (HW/SW) implementation of the vector median filter (VMF) using embedded system for impulsive noise suppression in color image. The hardware portion including VMF algorithm is implemented with fast parallel architectures directly in hardware using VHDL language. The remaining parts were realized in software using NIOS II softcore processor using muClinux as operating system. The results show that the use of codesign implementation improves 48 times the filtering speed compared to the software solution.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"54 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"HW/SW FPGA implementation of Vector Median Filter\",\"authors\":\"A. Boudabous, A. Ben Atitallah, P. Kadionik, L. Khriji, N. Masmoudi\",\"doi\":\"10.1109/RME.2007.4401821\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we present an efficient hardware/software (HW/SW) implementation of the vector median filter (VMF) using embedded system for impulsive noise suppression in color image. The hardware portion including VMF algorithm is implemented with fast parallel architectures directly in hardware using VHDL language. The remaining parts were realized in software using NIOS II softcore processor using muClinux as operating system. The results show that the use of codesign implementation improves 48 times the filtering speed compared to the software solution.\",\"PeriodicalId\":118230,\"journal\":{\"name\":\"2007 Ph.D Research in Microelectronics and Electronics Conference\",\"volume\":\"54 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-07-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 Ph.D Research in Microelectronics and Electronics Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RME.2007.4401821\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 Ph.D Research in Microelectronics and Electronics Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RME.2007.4401821","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this paper, we present an efficient hardware/software (HW/SW) implementation of the vector median filter (VMF) using embedded system for impulsive noise suppression in color image. The hardware portion including VMF algorithm is implemented with fast parallel architectures directly in hardware using VHDL language. The remaining parts were realized in software using NIOS II softcore processor using muClinux as operating system. The results show that the use of codesign implementation improves 48 times the filtering speed compared to the software solution.
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