PS-ORAM:对NVM上无关内存的高效崩溃一致性支持

Gang Liu, KenLi Li, Zheng Xiao, Rujia Wang
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引用次数: 7

摘要

遗忘RAM (ORAM)是一种可验证的安全原语,用于防止内存总线上的访问模式泄漏。通过随机重新映射数据块和访问冗余块,ORAM可以防止通过ob-fuscation导致访问模式泄漏。字节可寻址非易失性内存(NVM)被认为是主存的候选,因为它具有更好的可伸缩性、竞争性性能和持久的数据存储。虽然之前有很多工作集中在提高ORAM在传统的基于dram的内存系统上的性能上,但当内存技术转向使用NVM时,为了安全性、正确性和性能,需要确保一个高效的崩溃一致的ORAM。对ORAM系统直接使用传统的基于软件的崩溃一致性支持不仅成本高,而且不安全。在这项工作中,我们研究了如何在基于nvm的存储系统中持久化ORAM结构。为了在不破坏ORAM系统安全性和性能的情况下支持崩溃一致性,我们提出了PS-ORAM。PS-ORAM由一种新颖的ORAM控制器设计和一组支持崩溃一致性的ORAM访问协议组成。我们在不支持崩溃一致性的系统下对PS-ORAM进行了评估,非递归和递归PS-ORAM仅产生4.29%和3.65%的额外性能开销。结果表明,PS-ORAM不仅以最小的性能和硬件开销支持有效的崩溃一致性,而且对NVM寿命也很友好。
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PS-ORAM: efficient crash consistency support for oblivious RAM on NVM
Oblivious RAM (ORAM) is a provable secure primitive to prevent access pattern leakage on the memory bus. By randomly remapping the data blocks and accessing redundant blocks, ORAM prevents access pattern leakage through ob-fuscation. Byte-addressable non-volatile memory (NVM) is considered as the candidate for main memory due to its better scalability, competitive performance, and persistent data store. While there is much prior work focusing on improving ORAM's performance on the conventional DRAM-based memory system, when the memory technology shifts to use NVM, ensuring an efficient crash-consistent ORAM is needed for security, correctness, and performance. Directly using traditional software-based crash consistency support for ORAM system is not only expensive but also insecure. In this work, we study how to persist ORAM construction with an NVM-based memory system. To support crash consistency without damaging ORAM system security and compromising the performance, we propose PS-ORAM. PS-ORAM consists of a novel ORAM controller design and a set of ORAM access protocols that support crash consistency. We evaluate PS-ORAM with the system without crash consistency support, non-recursive and recursive PS-ORAM only incurs 4.29% and 3.65% additional performance overhead. The results show that PS-ORAM not only supports effective crash consistency with minimal performance and hardware overhead but also is friendly to NVM lifetime.
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