The Source Sensed Sram (S3) Cell

This paper proposes a new SRAM cell topology for full CMOS applications that relaxes interconnect density, lowers word line capacitance and reduces cell data access delays. This is achieved by replacing the conventional differential bit lines and access transmission gates with a single ended sensing scheme via the cell ground bus. It is ideally suited for multiported embedded ASIC memories where logic based technologies limit exotic approaches. Read word line loading is reduced by 1/2 and traditional read bit lines are. eliminated, relaxing the wiring pitch while reducing inter-signal cross coupling.