1.9 GHz 1.05V 16-bit RISC core for high density and low power operation in 28nm technology

Currently the advancement in widespread use of portable devices significantly increases importance of low power design of ICs using different low power techniques, such as power gating, multi voltage etc. Most of these techniques rely on different supply schemes for different areas and blocks of an IC to reduce dynamic and/or static (leakage) power. Thus these techniques are mostly applicable to Systems-On-Chip (SoCs) and their components, such as analog IPs and digital cores. This paper presents area and power optimization approach implemented on simple RISC core ready to be integrated into SoC. Proposed approach uses combination of several low power techniques to achieve desired result for custom-developed RISC core. Results present significant power reduction with acceptable high performance.