H. Noguchi, K. Ikegami, N. Shimomura, T. Tanamoto, J. Ito, S. Fujita
{"title":"高可靠性和低功耗的非易失性缓存存储器与先进的垂直STT-MRAM高性能CPU","authors":"H. Noguchi, K. Ikegami, N. Shimomura, T. Tanamoto, J. Ito, S. Fujita","doi":"10.1109/VLSIC.2014.6858403","DOIUrl":null,"url":null,"abstract":"This paper presents a novel nonvolatile last level cache (LLC) based on the advanced perpendicular STT-MRAM to reduce the total power consumption of LLC. The presented LLC has novel readout circuit with the dual-sensing salvation scheme that enhances reliability of STT-MRAM along with typical error-correcting code (ECC). The comparison of CPU performance per power with SRAM-based, embedded DRAM and conventional STT-MRAM-based LLCs indicates that the presented novel nonvolatile LLC is the most suitable for large LLC.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"58","resultStr":"{\"title\":\"Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU\",\"authors\":\"H. Noguchi, K. Ikegami, N. Shimomura, T. Tanamoto, J. Ito, S. Fujita\",\"doi\":\"10.1109/VLSIC.2014.6858403\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a novel nonvolatile last level cache (LLC) based on the advanced perpendicular STT-MRAM to reduce the total power consumption of LLC. The presented LLC has novel readout circuit with the dual-sensing salvation scheme that enhances reliability of STT-MRAM along with typical error-correcting code (ECC). The comparison of CPU performance per power with SRAM-based, embedded DRAM and conventional STT-MRAM-based LLCs indicates that the presented novel nonvolatile LLC is the most suitable for large LLC.\",\"PeriodicalId\":381216,\"journal\":{\"name\":\"2014 Symposium on VLSI Circuits Digest of Technical Papers\",\"volume\":\"42 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-06-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"58\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 Symposium on VLSI Circuits Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2014.6858403\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 Symposium on VLSI Circuits Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2014.6858403","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU
This paper presents a novel nonvolatile last level cache (LLC) based on the advanced perpendicular STT-MRAM to reduce the total power consumption of LLC. The presented LLC has novel readout circuit with the dual-sensing salvation scheme that enhances reliability of STT-MRAM along with typical error-correcting code (ECC). The comparison of CPU performance per power with SRAM-based, embedded DRAM and conventional STT-MRAM-based LLCs indicates that the presented novel nonvolatile LLC is the most suitable for large LLC.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
