Hsie-Chia Chang, Chih-Yu Chen, Shu-Hui Tsai, Chen-Yi Lee
{"title":"一种采用分解欧几里得算法的Reed-Solomon解码器","authors":"Hsie-Chia Chang, Chih-Yu Chen, Shu-Hui Tsai, Chen-Yi Lee","doi":"10.1109/MWSCAS.2000.951634","DOIUrl":null,"url":null,"abstract":"A (204, 188) Reed-Solomon decoder for DVB application is presented. The RS decoder features an area-efficient key equation solver using a novel decomposed Euclidean algorithm. We implement the RS decoder using 0.35/spl mu/m CMOS IP4M standard cells, where the total gate count is about 16K/spl sim/17K. Test results show that the RS decoder chip can run up to 87MHz.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A (204,188) Reed-Solomon decoder using decomposed Euclidean algorithm\",\"authors\":\"Hsie-Chia Chang, Chih-Yu Chen, Shu-Hui Tsai, Chen-Yi Lee\",\"doi\":\"10.1109/MWSCAS.2000.951634\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A (204, 188) Reed-Solomon decoder for DVB application is presented. The RS decoder features an area-efficient key equation solver using a novel decomposed Euclidean algorithm. We implement the RS decoder using 0.35/spl mu/m CMOS IP4M standard cells, where the total gate count is about 16K/spl sim/17K. Test results show that the RS decoder chip can run up to 87MHz.\",\"PeriodicalId\":437349,\"journal\":{\"name\":\"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-08-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2000.951634\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2000.951634","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A (204,188) Reed-Solomon decoder using decomposed Euclidean algorithm
A (204, 188) Reed-Solomon decoder for DVB application is presented. The RS decoder features an area-efficient key equation solver using a novel decomposed Euclidean algorithm. We implement the RS decoder using 0.35/spl mu/m CMOS IP4M standard cells, where the total gate count is about 16K/spl sim/17K. Test results show that the RS decoder chip can run up to 87MHz.