{"title":"高速乘法器设计采用多输入计数器和压缩电路","authors":"Mayur Mehta, Vijay Parmar, E. Swartzlander","doi":"10.1109/ARITH.1991.145532","DOIUrl":null,"url":null,"abstract":"The design of a fast multiplier implemented using either","PeriodicalId":190650,"journal":{"name":"[1991] Proceedings 10th IEEE Symposium on Computer Arithmetic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"92","resultStr":"{\"title\":\"High-speed multiplier design using multi-input counter and compressor circuits\",\"authors\":\"Mayur Mehta, Vijay Parmar, E. Swartzlander\",\"doi\":\"10.1109/ARITH.1991.145532\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The design of a fast multiplier implemented using either\",\"PeriodicalId\":190650,\"journal\":{\"name\":\"[1991] Proceedings 10th IEEE Symposium on Computer Arithmetic\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-06-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"92\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1991] Proceedings 10th IEEE Symposium on Computer Arithmetic\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ARITH.1991.145532\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1991] Proceedings 10th IEEE Symposium on Computer Arithmetic","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ARITH.1991.145532","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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